AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 532

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 37-3.
Note:
Warning: In PDC mode, reading to
532
Encryption/Decryption
Encrypted/Decrypted
Data Result Location
Clearing Condition
DATRDY Flag
1. Depending on the mode, there are other ways of clearing the DATRDY flag.
End of
AT91SAM7XC512/256/128 Preliminary
541.
Last Output Mode Behavior versus Start Modes
(1)
Figure 37-4. PDC Mode with LOD = 1:
Table 37-3
Data Register must be
At least one Output
In the Output Data
ENDTX (or TXBUFE)
Registers
LOD = 0
DATRDY
the Output Data
read
summarizes the different cases.
Manual and Auto Modes
DATRDY
Enable PDC Channels (only Transmit Channels)
registers before the last data transfer may lead to unpredictable result.
Register must be written
At least one Input Data
In the Output Data
Multiple Encryption or Decryption Process
Registers
LOD = 1
DATRDY
ENDRX (or RXBUFF)
Receive Pointer
specified in the
See “TDES Interrupt Status Register” on page
At the address
(TDES_RPR)
Not used
LOD = 0
Register
PDC Mode
Managed by the PDC
ENDTX (or TXBUFE)
In the Output Data
6209F–ATARM–17-Feb-09
then DATRDY
Registers
LOD = 1