LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 132

• Manufacturer Part Number: LPC1343FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 40
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4945; 935289652151

NXP Semiconductors
UM10375
User manual
9.10.1.2 USB Device Interrupt Enable register (USBDevIntEn - 0x4002 0004)
9.10.1.3 USB Device Interrupt Clear register (USBDevIntClr - 0x4002 0008)
Table 156. USB Device Interrupt Status register (USBDevIntSt - address 0x4002 0000) bit
Writing a one to a bit in this register enables the corresponding bit in USBDevIntSt to
generate an external interrupt when set. If it’s not set, no external interrupt is generated,
but the interrupt will still be held in the Device Interrupt Status register.
Table 157. USB Device Interrupt Enable register (USBDevIntEn - address 0x4002 0004) bit
Writing one to a bit in this register clears the corresponding bit in USBDevIntSt. Writing a
zero has no effect.
USBDevIntClr is a write only register.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
31:14 -
Bit
31:0
Symbol
FRAME
EP0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
DEV_STAT
CC_EMPTY The command code register (USBCmdCode) is empty (New
CD_FULL
RxENDPKT The current packet in the endpoint buffer is transferred to the
TxENDPKT
Symbol
See
description
description
Table 155
All information provided in this document is subject to legal disclaimers.
Description
The frame interrupt occurs every 1 ms. This is used in
isochronous packet transfers.
USB core interrupt for physical endpoint 0.
USB core interrupt for physical endpoint 1.
USB core interrupt for physical endpoint 2.
USB core interrupt for physical endpoint 3.
USB core interrupt for physical endpoint 4.
USB core interrupt for physical endpoint 5.
USB core interrupt for physical endpoint 6.
USB core interrupt for physical endpoint 7.
Set when USB Bus reset, USB suspend change, or Connect
change event occurs. Refer to
(Command: 0xFE, Data: write 1 byte)” on page
command can be written).
Command data register (USBCmdData) is full (Data can be read
now).
CPU.
The number of data bytes transferred to the endpoint buffer
equals the number of bytes programmed in the TxPacket length
register (USBTxPLen).
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Value
0
1
Rev. 2 — 7 July 2010
Description
No interrupt is generated.
An interrupt will be generated when the corresponding
bit in the Device Interrupt Status (USBDevIntSt)
register
(Table
Chapter 9: LPC13xx USB device controller
155) is set.
Section 9.11.7 “Set Device Status
144.
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
0
0
1
0
0
0
NA
0
Reset
value
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