LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 193
LPC1343FBD48,151
Manufacturer Part Number
LPC1343FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
40
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
42
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4945
935289652151
935289652151
Available stocks
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Price
Company:
Part Number:
LPC1343FBD48,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
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Manufacturer:
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Table 209. Register overview: I
[1]
UM10375
User manual
Name
I2C0ADR1
I2C0ADR2
I2C0ADR3
I2C0DATA_
BUFFER
I2C0MASK0
I2C0MASK1
I2C0MASK2
I2C0MASK3
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
12.8.1 I
Access Address
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
The I2CONSET registers control setting of bits in the I2CON register that controls
operation of the I
corresponding bit in the I
Table 210. I
Bit
1:0
2
3
4
5
6
31:7 -
2
offset
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
C Control Set register (I2C0CONSET - 0x4000 0000)
Symbol
-
AA
SI
STO
STA
I2EN
2
C (base address 0x4000 0000)
2
C Control Set register (I2C0CONSET - address 0x4000 0000) bit description
Description
I2C Slave Address Register 1. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
I2C Slave Address Register 2. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
I2C Slave Address Register 3. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
Data buffer register. The contents of the 8 MSBs of the I2DAT shift
register will be transferred to the DATA_BUFFER automatically after
every nine bits (8 bits of data plus ACK or NACK) has been received on
the bus.
I2C Slave address mask register 0. This mask register is associated
with I2ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 1. This mask register is associated
with I2ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 2. This mask register is associated
with I2ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 3. This mask register is associated
with I2ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
All information provided in this document is subject to legal disclaimers.
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Assert acknowledge flag.
I
STOP flag.
START flag.
I
Reserved. The value read from a reserved bit is not defined.
2
2
2
C interrupt flag.
C interface enable.
C interface. Writing a one to a bit of this register causes the
Rev. 2 — 7 July 2010
2
C control register to be set. Writing a zero has no effect.
2
2
2
C interface in slave mode, and is not used in master
C interface in slave mode, and is not used in master
C interface in slave mode, and is not used in master
…continued
Chapter 12: LPC13xx I2C-bus controller
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
NA
0
0
0
0
-
Reset
value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
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