LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 180
LPC1343FBD48,151
Manufacturer Part Number
LPC1343FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
40
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
42
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4945
935289652151
935289652151
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FBD48,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC1343FBD48,151
Manufacturer:
NXP/恩智浦
Quantity:
20 000
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UM10375
User manual
11.6.14 Auto-baud modes
The U0ACR AutoRestart bit can be used to automatically restart baud rate measurement
if a time-out occurs (the rate measurement counter overflows). If this bit is set, the rate
measurement will restart at the next falling edge of the UART Rx pin.
The auto-baud function can generate two interrupts.
The auto-baud interrupts have to be cleared by setting the corresponding U0ACR
ABTOIntClr and ABEOIntEn bits.
The fractional baud rate generator must be disabled (DIVADDVAL = 0) during auto-baud.
Also, when auto-baud is used, any write to U0DLM and U0DLL registers should be done
before U0ACR register write. The minimum and the maximum baud rates supported by
UART are function of UART_PCLK, number of data bits, stop bits and parity bits.
When the software is expecting an ”AT" command, it configures the UART with the
expected character format and sets the U0ACR Start bit. The initial values in the divisor
latches U0DLM and U0DLM don‘t care. Because of the ”A" or ”a" ASCII coding
(”A" = 0x41, ”a" = 0x61), the UART Rx pin sensed start bit and the LSB of the expected
character are delimited by two falling edges. When the U0ACR Start bit is set, the
auto-baud protocol will execute the following phases:
1. On U0ACR Start bit setting, the baud rate measurement counter is reset and the
2. A falling edge on UART Rx pin triggers the beginning of the start bit. The rate
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with
4. During the receipt of the start bit (and the character LSB for Mode = 0), the rate
5. If Mode = 0, the rate counter will stop on next falling edge of the UART Rx pin. If
•
•
ratemin
The U0IIR ABTOInt interrupt will get set if the interrupt is enabled (U0IER ABToIntEn
is set and the auto-baud rate measurement counter overflows).
The U0IIR ABEOInt interrupt will get set if the interrupt is enabled (U0IER ABEOIntEn
is set and the auto-baud has completed successfully).
UART U0RSR is reset. The U0RSR baud rate is switched to the highest rate.
measuring counter will start counting UART_PCLK cycles.
the frequency of the UART input clock, guaranteeing the start bit is stored in the
U0RSR.
counter will continue incrementing with the pre-scaled UART input clock
(UART_PCLK).
Mode = 1, the rate counter will stop on the next rising edge of the UART Rx pin.
=
2 P
------------------------ -
16 2 15
All information provided in this document is subject to legal disclaimers.
× CLK
×
≤
Rev. 2 — 7 July 2010
UART baudrate
≤
----------------------------------------------------------------------------------------------------------- -
16
×
(
2
+
databits
PCLK
+
paritybits
Chapter 11: LPC13xx UART
+
stopbits
UM10375
© NXP B.V. 2010. All rights reserved.
)
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