LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 240

• Manufacturer Part Number: LPC1343FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 40
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4945; 935289652151

NXP Semiconductors
13.8 Functional description
UM10375
User manual
13.7.9 SSP0 Interrupt Clear Register (SSP0ICR - 0x4004 0020)
13.8.1 Texas Instruments synchronous serial frame format
Table 242: SSP0 Masked Interrupt Status register (SSP0MIS -address 0x4004 001C) bit
Software can write one or more one(s) to this write-only register, to clear the
corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO, or disabled by
clearing the corresponding bit in SSP0IMSC.
Table 243: SSP0 interrupt Clear Register (SSP0ICR - address 0x4004 0020) bit description
Figure 37
by the SSP module.
Bit
0
1
2
3
31:4
Bit
0
1
31:2
Symbol
RORMIS
RTMIS
RXMIS
TXMIS
-
Symbol
RORIC
RTIC
-
shows the 4-wire Texas Instruments synchronous serial frame format supported
description
All information provided in this document is subject to legal disclaimers.
Description
This bit is 1 if another frame was completely received while the
RxFIFO was full, and this interrupt is enabled.
This bit is 1 if the Rx FIFO is not empty, has not been read for
a time-out period, and this interrupt is enabled. The time-out
period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR
× [SCR+1]).
This bit is 1 if the Rx FIFO is at least half full, and this interrupt
is enabled.
This bit is 1 if the Tx FIFO is at least half empty, and this
interrupt is enabled.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
Writing a 1 to this bit clears the “frame was received when
RxFIFO was full” interrupt.
Writing a 1 to this bit clears the Rx FIFO was not empty and
has not been read-bit for a time-out period interrupt. The
time-out period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR
× [SCR+1]).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 2 — 7 July 2010
Chapter 13: LPC13xx SSP
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0
0
0
0
NA
Reset value
NA
NA
NA
242 of 333