LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 208
LPC1343FBD48,151
Manufacturer Part Number
LPC1343FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
40
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
42
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4945
935289652151
935289652151
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FBD48,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC1343FBD48,151
Manufacturer:
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Quantity:
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UM10375
User manual
12.11.1 Master Transmitter mode
Table 224. Abbreviations used to describe an I
In
The numbers in the circles show the status code held in the I2STAT register. At these
points, a service routine must be executed to continue or complete the serial transfer.
These service routines are not critical since the serial transfer is suspended until the serial
interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in I2STAT is used to branch to
the appropriate service routine. For each status code, the required software action and
details of the following serial transfer are given in tables from
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver
(see
initialized as follows:
Table 225. I2CONSET used to initialize Master Transmitter mode
The I
set to logic 1 to enable the I
acknowledge its own slave address or the General Call address in the event of another
device becoming master of the bus. In other words, if AA is reset, the I
enter a slave mode. STA, STO, and SI must be reset.
Abbreviation
S
SLA
R
W
A
A
Data
P
Bit
Symbol
Value
Figure 30
Figure
2
C rate must also be configured in the I2SCLL and I2SCLH registers. I2EN must be
7
-
-
30). Before the master transmitter mode can be entered, I2CON must be
to
Figure
All information provided in this document is subject to legal disclaimers.
6
I2EN
1
34, circles are used to indicate when the serial interrupt flag is set.
Explanation
START Condition
7-bit slave address
Read bit (HIGH level at SDA)
Write bit (LOW level at SDA)
Acknowledge bit (LOW level at SDA)
Not acknowledge bit (HIGH level at SDA)
8-bit data byte
STOP condition
Rev. 2 — 7 July 2010
2
C block. If the AA bit is reset, the I
5
STA
0
4
STO
0
2
C operation
Chapter 12: LPC13xx I2C-bus controller
3
SI
0
2
AA
x
Table 228
2
C block will not
2
UM10375
1
-
-
C interface cannot
© NXP B.V. 2010. All rights reserved.
to
Table
232.
0
-
-
210 of 333
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