LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 198
LPC1343FBD48,151
Manufacturer Part Number
LPC1343FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
40
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
42
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4945
935289652151
935289652151
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FBD48,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC1343FBD48,151
Manufacturer:
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Quantity:
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UM10375
User manual
12.8.7.1 Interrupt in Monitor mode
Table 218. I
[1]
Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if
the module is NOT in monitor mode).
All interrupts will occur as normal when the module is in monitor mode. This means that
the first interrupt will occur when an address-match is detected (any address received if
the MATCH_ALL bit is set, otherwise an address matching one of the four address
registers).
Bit
0
1
2
31:3 -
When the ENA_SCL bit is cleared and the I
time becomes important. To give the part more time to respond to an I
DATA _BUFFER register is used
time.
Symbol
MM_ENA
ENA_SCL
MATCH_ALL
2
C Monitor mode control register (I2C0MMCTRL - 0x4000 001C) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
-
Rev. 2 — 7 July 2010
Monitor mode enable.
Monitor mode disabled.
The I
SDA output will be forced high. This will prevent the I
module from outputting data of any kind (including ACK)
onto the I
Depending on the state of the ENA_SCL bit, the output may
be also forced high, preventing the module from having
control over the I
SCL output enable.
When this bit is cleared to ‘0’, the SCL output will be forced
high when the module is in monitor mode. As described
above, this will prevent the module from having any control
over the I
When this bit is set, the I
control over the clock line that it would in normal operation.
This means that, acting as a slave peripheral, the I
module can “stretch” the clock line (hold it low) until it has
had time to respond to an I
Select interrupt register match.
When this bit is cleared, an interrupt will only be generated
when a match occurs to one of the (up-to) four address
registers described above. That is, the module will respond
as a normal slave as far as address-recognition is
concerned.
When this bit is set to ‘1’ and the I
interrupt will be generated on ANY address received. This
will enable the part to monitor all traffic on the bus.
Reserved. The value read from reserved bits is not defined.
(Section
2
C module will enter monitor mode. In this mode the
2
2
C data bus.
C clock line.
12.8.9) to hold received data for a full 9-bit word transmission
2
C no longer has the ability to stall the bus, interrupt response
2
C clock line.
Chapter 12: LPC13xx I2C-bus controller
2
C module may exercise the same
2
C interrupt.
2
C is in monitor mode, an
2
C interrupt under these conditions, a
[1]
UM10375
© NXP B.V. 2010. All rights reserved.
2
C
2
C
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0
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