LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 191

• Manufacturer Part Number: LPC1343FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 40
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4945; 935289652151

NXP Semiconductors
UM10375
User manual
12.5.1 I
The I
master receiver mode, slave transmitter mode and slave receiver mode.
The I
power off to the ARM Cortex-M3 without interfering with other devices on the same
I
Fast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I
products which NXP Semiconductors is now providing.
In order to use Fast-Mode Plus, the I
IOCONFIG register block, see
400 kHz and up to 1 MHz may be selected.
2
2
Fig 21. I
•
•
C-bus.
C Fast-mode Plus
Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte.
Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” is returned. The master device generates all
of the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a Repeated START condition. Since a Repeated
START condition is also the beginning of the next serial transfer, the I
be released.
2
2
C interface is byte oriented and has four operating modes: master transmitter mode,
C interface complies with the entire I
I
2
C-bus
2
C-bus configuration
SDA
All information provided in this document is subject to legal disclaimers.
LPC13xx
SCL
Rev. 2 — 7 July 2010
Table 102
pull-up
resistor
OTHER DEVICE WITH
2
C pins must be properly configured in the
I
2
C INTERFACE
and
2
C specification, supporting the ability to turn
Table
Chapter 12: LPC13xx I2C-bus controller
pull-up
resistor
103. In Fast-mode Plus, rates above
OTHER DEVICE WITH
I
2
C INTERFACE
UM10375
© NXP B.V. 2010. All rights reserved.
2
C bus will not
2
SDA
SCL
C-bus
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