LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 182

• Manufacturer Part Number: LPC1343FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 40
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4945; 935289652151

NXP Semiconductors
UM10375
User manual
11.6.15.1 Baud rate calculation
Table 202. UART Fractional Divider Register (U0FDR - address 0x4000 8028) bit description
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART disabled making sure that UART is
fully software and hardware compatible with UARTs not equipped with this feature.
The UART baud rate can be calculated as:
Where UART_PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART
baud rate divider registers, and DIVADDVAL and MULVAL are UART fractional baud rate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
The value of the U0FDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.
If the U0FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
UART can operate with or without using the Fractional Divider. In real-life applications it is
likely that the desired baud rate can be achieved using several different Fractional Divider
settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a
relative error of less than 1.1% from the desired one.
Bit
3:0
7:4
31:8
1. 1 ≤ MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 14
3. DIVADDVAL< MULVAL
Function
DIVADDVAL
MULVAL
-
UART
All information provided in this document is subject to legal disclaimers.
baudrate
Value Description
0
1
NA
Rev. 2 — 7 July 2010
=
Baud rate generation pre-scaler divisor value. If this field is
0, fractional baud rate generator will not impact the UART
baud rate.
Baud rate pre-scaler multiplier value. This field must be
greater or equal 1 for UART to operate properly,
regardless of whether the fractional baud rate generator is
used or not.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
----------------------------------------------------------------------------------------------------------------------------------
16
×
(
256
×
U0DLM
+
PCLK
U0DLL
)
×
Chapter 11: LPC13xx UART
⎛
⎝
1
+
DivAddVal
---------------------------- -
MulVal
UM10375
© NXP B.V. 2010. All rights reserved.
⎞
⎠
184 of 333
Reset
value
0
1
0
(3)