LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 192

• Manufacturer Part Number: LPC1343FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 40
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4945; 935289652151

NXP Semiconductors
12.6 Pin description
12.7 Clocking and power control
12.8 Register description
Table 209. Register overview: I
UM10375
User manual
Name
I2C0CONSET R/W
I2C0STAT
I2C0DAT
I2C0ADR0
I2C0SCLH
I2C0SCLL
I2C0CONCLR WO
I2C0MMCTRL R/W
Access Address
RO
R/W
R/W
R/W
R/W
Table 208. I
The I
IOCON_PIO0_5
these modes, the I
I
The clock to the I
Figure
(Table
Remark: Before accessing the I2C block, ensure that the I2C_RST_N bit (bit 1) in the
PRESETCTRL register
block.
Pin
SDA
SCL
2
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
C-bus specification.
2
C-bus pins must be configured through the IOCON_PIO0_4
23) for power savings.
3). This clock can be disabled through bit 5 in the SYSAHBCLKCTRL register
2
C (base address 0x4000 0000)
2
C-bus pin description
Description
I2C Control Set Register. When a one is written to a bit of this register,
the corresponding bit in the I
no effect on the corresponding bit in the I
I2C Status Register. During I
status codes that allow software to determine the next action needed.
I2C Data Register. During master or slave transmit mode, data to be
transmitted is written to this register. During master or slave receive
mode, data that has been received may be read from this register.
I2C Slave Address Register 0. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
SCH Duty Cycle Register High Half Word. Determines the high time of
the I
SCL Duty Cycle Register Low Half Word. Determines the low time of
the I
frequency generated by an I
mode.
I2C Control Clear Register. When a one is written to a bit of this register,
the corresponding bit in the I
has no effect on the corresponding bit in the I
Monitor mode control register.
Type
Input/Output
Input/Output
All information provided in this document is subject to legal disclaimers.
(Table
2
2
2
C-bus interface (PCLK_I2C) is provided by the system clock (see
C clock.
C clock. I2nSCLL and I2nSCLH together determine the clock
2
C-bus pins are open-drain outputs and fully compatible with the
103) registers for Standard/ Fast-mode or Fast-mode Plus. In
(Table
Rev. 2 — 7 July 2010
2
C interface in slave mode, and is not used in master
7) is set to 1. This de-asserts the reset signal to the I2C
Description
I
I
2
2
C-bus Serial Data
C-bus Serial Clock
2
2
2
C master and certain times used in slave
C control register is set. Writing a zero has
2
C control register is cleared. Writing a zero
C operation, this register provides detailed
Chapter 12: LPC13xx I2C-bus controller
2
C control register.
2
C control register.
(Table
UM10375
© NXP B.V. 2010. All rights reserved.
102) and
Reset
value
0x00
0xF8
0x00
0x00
0x04
0x04
NA
0x00
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