LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 218
LPC1343FBD48,151
Manufacturer Part Number
LPC1343FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
40
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
42
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4945
935289652151
935289652151
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FBD48,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC1343FBD48,151
Manufacturer:
NXP/恩智浦
Quantity:
20 000
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NXP Semiconductors
UM10375
User manual
Fig 32. Format and states in the Slave Receiver mode
reception of the own
Slave address and one
or more Data bytes all
are acknowledged
last data byte
received is Not
acknowledged
arbitration lost as
Master and addressed
as Slave
reception of the
General Call address
and one or more Data
bytes
last data byte is Not
acknowledged
arbitration lost as
Master and addressed
as Slave by General
Call
DATA
n
A
S
from Master to Slave
from Slave to Master
any number of data bytes and their associated Acknowledge bits
this number (contained in I2STA) corresponds to a defined state of the I
bus
All information provided in this document is subject to legal disclaimers.
GENERAL CALL
SLA
Rev. 2 — 7 July 2010
W
60H
68H
70h
78h
A
A
A
A
DATA
DATA
Chapter 12: LPC13xx I2C-bus controller
80H
90h
A
A
DATA
DATA
2
C
80H
88H
90h
98h
A
A
A
A
UM10375
P OR S
P OR S
P OR S
P OR S
© NXP B.V. 2010. All rights reserved.
A0H
A0H
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