ST10F269Z2Q3 STMicroelectronics, ST10F269Z2Q3 Datasheet - Page 114

• Manufacturer Part Number: ST10F269Z2Q3
• Description: IC FLASH MEM 256KBIT 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 0.3 V to 4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-2042

18 - SYSTEM RESET
18 - SYSTEM RESET
System reset initializes the MCU in a predefined
state. There are five ways to activate a reset state.
18.1 - Long Hardware Reset
The reset is triggered when RSTIN pin is pulled
low, then the MCU is immediately forced in reset
default state. It pulls low RSTOUT pin, it cancels
pending internal hold states if any, it aborts
external bus cycle, it switches buses (data,
address and control signals) and I/O pin drivers to
high-impedance, it pulls high PORT0 pins and the
reset sequence starts.
To get a long hardware reset, the duration of the
external RSTIN signal must be longer than 1040
TCL. The level of RPD pin is sampled during the
whole RSTIN pulse duration. A low level on RPD
Figure 54 : Asynchronous Reset Sequence External Fetch
Note: 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
114/184
Power-on reset
Long Hardware reset (synchronous & asynchronous)
Short Hardware reset (synchronous reset)
Watchdog Timer reset
Software reset
(f
CPU
= f
RSTIN
RPD
RSTOUT
PORT0
Internal reset
CPU Clock
ALE
RD
XTAL
/ 2), else it is 4 CPU clock cycles (8 TCL).
Reset Source
Reset Condition
Asynchronous
Reset Configuration
1
6 or 8 TCL
2
3
1)
4
5
The system start-up configuration is different for
each case as shown in Table 37.
Table 37 : Reset Event Definition
pin determines an asynchronous reset while a
high level leads to a synchronous reset.
Note
18.1.1 - Asynchronous Reset
Figure 54 and Figure 55 show asynchronous
reset condition (RPD pin is at low level).
5 TCL
Short-cut
Latching point of PORT0
for system start-up
configuration
SHWR
WDTR
PONR
LHWR
6
SWR
7
A reset can be entered as synchronous
and exit as asynchronous if V
drops below the RPD pin threshold
(typically 2.5V for V
pin is low or when RSTIN pin is internally
pulled low.
8
9
Power-on
t
4 TCL < t
WDT overflow
SRST execution
RSTIN
1st Instruction External Fetch
> 1040 TCL
RSTIN
EXTERNAL FETCH
Conditions
DD
< 1038 TCL
= 5V) when RSTIN
ST10F269
RPD
voltage