ST10F269Z2Q3 STMicroelectronics, ST10F269Z2Q3 Datasheet - Page 48

• Manufacturer Part Number: ST10F269Z2Q3
• Description: IC FLASH MEM 256KBIT 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 0.3 V to 4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-2042

8 - INTERRUPT SYSTEM
xxIC (yyyyh / zzh)
8.4 - Exception and Error Traps List
Table 8 shows all of the possible exceptions or error conditions that can arise during run-time:
Table 8 : Trap Priorities
*
48/184
Reset Functions:
Class A Hardware Traps:
Class B Hardware Traps:
Reserved
Software Traps
15
- All the class B traps have the same trap number (and vector) and the same lower priority compare to the class A traps and to the resets.
- Each class A traps has a dedicated trap number (and vector). They are prioritized in the second priority level.
- The resets have the highest priority level and the same trap number.
- The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced.
-
GLVL
ILVL
xxIE
xxIR
Bit
14
-
Exception Condition
Hardware Reset
Software Reset
Watchdog Timer Overflow
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Undefined Opcode
Protected Instruction Fault
Illegal word Operand Access
Illegal Instruction Access
Illegal External Bus Access
TRAP Instruction
13
-
Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
Interrupt Priority Level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
Interrupt Enable Control Bit (individually enables/disables a specific source)
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
12
-
11
-
10
-
UNDOPC
PRTFLT
ILLBUS
STKOF
STKUF
ILLOPA
ILLINA
9
-
Trap
Flag
NMI
SFR Area
8
-
STOTRAP
STUTRAP
NMITRAP
RESET
RESET
RESET
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
xxIR
Vector
RW
Trap
7
Function
xxIE
RW
6
[002Ch - 003Ch]
0000h – 01FCh
in steps of 4h
Location
00’0000h
00’0000h
00’0000h
00’0008h
00’0010h
00’0018h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
5
Vector
Any
4
ILVL
RW
3
[0Bh - 0Fh]
[00h - 7Fh]
Number
Reset Value: - - 00h
Trap
0Ah
0Ah
0Ah
0Ah
0Ah
00h
00h
00h
02h
04h
06h
Any
2
ST10F269
1
GLVL
Priority
Current
Priority
RW
Trap*
CPU
III
III
III
II
II
II
I
I
I
I
I
0