ST10F269Z2Q3 STMicroelectronics, ST10F269Z2Q3 Datasheet - Page 175

• Manufacturer Part Number: ST10F269Z2Q3
• Description: IC FLASH MEM 256KBIT 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 0.3 V to 4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-2042

ST10F269
Note: 1. Timing guaranteed by design.
The formula for SSC Clock Cycle time is : t
Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer
Figure 82 : SSC Master Timing
Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge
21.4.14.2 Slave mode
V
t
t
318p
t
t
t
t
t
t
t
t
CC
317p
Symbol
318
Symbol
310
311
312
313
314
315
316
= 5V ±10%, V
1
(drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO =
0b).
2. The bit timing is repeated for all bits to be transmitted or received.
SCLK
MTSR
MRST
SR Read data hold time after latch edge,
SR SSC clock cycle time
SR SSC clock high time
SR SSC clock low time
SR SSC clock rise time
SR SSC clock fall time
CC Write data valid after shift edge
CC Write data hold after shift edge
SR Read data setup time before latch
SR Read data hold time after latch edge,
phase error detection off (SSCPEN = 0)
edge,
(SSCPEN = 1)
phase
(SSCPEN = 1)
1)
SS
phase
error
= 0V, CPU clock = 40MHz, T
Parameter
Parameter
t
305
1st.In Bit
error
t
307
t
300
1st Out Bit
detection
t
308
detection
t
t
301
305
t
304
300
2nd Out Bit
on
on
t
2nd.In Bit
302
Maximum Baud rate=6.25MBd
= 4 TCL * (<SSCBR> + 1)
Maximum Baud rate=10MBd
Minimum
Minimum
A
41.25
(<SSCBR> = 0001h)
(<SSCBR> = 0001h)
100
40
40
62
87
= -40 to +125°C, C
t
–
–
–
0
303
t
306
2)
Maximum
Maximum
100
10
10
39
–
–
–
–
–
–
t
L
305
= 50pF (PQFP144 devices)
t
Last.In Bit
307
(<SSCBR>=0001h-FFFFh) Symb
Last Out Bit
(<SSCBR>=0001h-FFFFh)
2TCL + 10
t
t
4TCL + 12
6TCL + 12
Minimum
Minimum
310
310
t
308
8 TCL
Variable Baud rate
Variable Baud rate
/2 - 10
/2 - 10
–
–
–
0
262144 TCL
2 TCL + 14
Maximum
Maximum
10
10
–
–
–
–
–
–
175/184
Unit
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
318
ol