ST10F269Z2Q3 STMicroelectronics, ST10F269Z2Q3 Datasheet - Page 134
![IC FLASH MEM 256KBIT 144-PQFP](/photos/12/15/121566/497-144-pqfp_series_sml.jpg)
ST10F269Z2Q3
Manufacturer Part Number
ST10F269Z2Q3
Description
IC FLASH MEM 256KBIT 144-PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F269Z2Q3.pdf
(184 pages)
Specifications of ST10F269Z2Q3
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-QFP
Processor Series
ST10F26x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN, SSC, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
2 x 16 bit
Operating Supply Voltage
0.3 V to 4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit x 10 bit
Cpu Family
ST10
Device Core Size
16b
Frequency (max)
40MHz
Total Internal Ram Size
12KB
# I/os (max)
111
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
CISC/RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-2042
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F269Z2Q3
Manufacturer:
INFINEON
Quantity:
1 443
Company:
Part Number:
ST10F269Z2Q3
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST10F269Z2Q3
Manufacturer:
ST
Quantity:
20 000
20 - SPECIAL FUNCTION REGISTER OVERVIEW
BUSCON4 (FF1Ah / 8Dh)
Notes: 1. BTYP (bit 6 and 7) are set according to the configuration of the bit l6 and l7 of PORT0 latched at the end of the reset sequence.
134/184
CSWEN4 CSREN4 RDYPOL4 RDYEN4
MCTC
RWDCx
MTTCx
BTYP
ALECTLx
BUSACTx
RDYENx
RDYPOLx
CSRENx
CSWENx
RW
15
2. BUSCON0 is initialized with 0000h, if EA pin is high during reset. If EA pin is low during reset, bit BUSACT0 and ALECTRL0 are
set (’1’) and bit field BTYP is loaded with the bus configuration selected via PORT0.
RW
14
RW
13
RW
12
Memory Cycle Time Control (Number of memory cycle time wait states)
0 0 0 0: 15 wait states (Nber = 15 - [MCTC])
. . .
1 1 1 1: No wait state
Read/Write Delay Control for BUSCONx
‘0’: With read/write delay: activate command 1 TCL after falling edge of ALE
‘1’: No read/write delay: activate command with falling edge of ALE
Memory Tristate Time Control
‘0’: 1 wait state
‘1’: No wait state
External Bus Configuration
0 0: 8-bit Demultiplexed Bus
0 1: 8-bit Multiplexed Bus
1 0: 16-bit Demultiplexed Bus
1 1: 16-bit Multiplexed Bus
Note: For BUSCON0, BTYP bit-field is defined via PORT0 during reset.
ALE Lengthening Control
‘0’: Normal ALE signal
‘1’: Lengthened ALE signal
Bus Active Control
‘0’: External bus disabled
‘1’: External bus enabled (within the respective address window, see
ADDRSEL)
READY Input Enable
‘0’: External bus cycle is controlled by bit field MCTC only
‘1’: External bus cycle is controlled by the READY input signal
Ready Active Level Control
‘0’: Active level on the READY pin is low, bus cycle terminates with a ‘0’ on
READY pin,
‘1’: Active level on the READY pin is high, bus cycle terminates with a ‘1’ on
READY pin.
Read Chip Select Enable
‘0’: The CS signal is independent of the read command (RD)
‘1’: The CS signal is generated for the duration of the read command
Write Chip Select Enable
‘0’: The CS signal is independent of the write command (WR,WRL,WRH)
‘1’: The CS signal is generated for the duration of the write command
11
-
BUSACT4
RW
10
SFR
ALECTL4
RW
9
8
-
7
BTYP
RW
6
MTTC4 RWDC4
RW
5
RW
4
Reset Value: 0000h
3
ST10F269
MCTC
2
RW
1
0