MC9S12C32CFAE25 Freescale Semiconductor, MC9S12C32CFAE25 Datasheet

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MC9S12C Family MC9S12GC Family Reference Manual HCS12 Microcontrollers MC9S12C128 Rev 01.24 05/2010 freescale.com ...

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To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ ...

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... Kbyte Flash Module (S12FTS64KV4 537 Chapter 20 96 Kbyte Flash Module (S12FTS96KV1 575 Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1 613 Appendix A Electrical Characteristics 647 Appendix B Emulation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 Appendix C Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24 3 ...

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... Appendix E Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 4 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

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... Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.7.8 MODRR Register Port T And Port P Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.7.9 Port AD Dependency On PIM And ATD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.8 Recommended Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Port Integration Module (PIM9C32) Block Description 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Freescale Semiconductor Chapter SS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Chapter 2 MC9S12C-Family / MC9S12GC-Family Rev 01.24 5 ...

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... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.4.1 Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.4.2 Stretched Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6 Chapter 3 Chapter 4 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

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... Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 6.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 6.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Freescale Semiconductor Chapter 5 Chapter 6 MC9S12C-Family / MC9S12GC-Family Rev 01.24 7 ...

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... AN2 / PAD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2.7 AN1 / PAD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2.8 AN0 / PAD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2 225 8.2. DDA SSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 8 Chapter 7 Chapter 8 Block Description MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

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... Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 284 9.5.3 Power-On Reset, Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 9.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 9.6.1 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 9.6.2 PLL Lock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 9.6.3 Self-Clock Mode Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Freescale Semiconductor Chapter 9 — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . . . . 253 MC9S12C-Family / MC9S12GC-Family Rev 01.24 9 ...

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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.4.1 Amplitude Limitation Control (ALC 346 11.4.2 Clock Monitor (CM 346 11.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 10 Chapter 10 Chapter 11 — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . 344 Chapter 12 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

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... Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 13.4.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 13.4.5 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 13.4.6 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 13.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 13.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 13.5.2 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 13.5.3 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Freescale Semiconductor Chapter 13 Block Description MC9S12C-Family / MC9S12GC-Family Rev 01.24 11 ...

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... IOC3 — Input Capture and Output Compare Channel 3 Pin . . . . . . . . . . . . . . . . . . . . 438 15.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin . . . . . . . . . . . . . . . . . . . . 439 15.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin . . . . . . . . . . . . . . . . . . . . 439 12 Chapter 14 Chapter 15 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

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... POR — Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 16.4.6 LVR — Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 16.4.7 CTRL — Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 16.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 16.5.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 16.5.2 Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 Freescale Semiconductor Chapter 16 Block Description — Regulator Output2 (PLL 466 MC9S12C-Family / MC9S12GC-Family Rev 01.24 ...

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... Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 18.4.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 18.4.3 Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 18.4.4 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 18.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 64 Kbyte Flash Module (S12FTS64KV4) 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 19.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 19.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 14 Chapter 17 Chapter 18 Chapter 19 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

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... Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 21.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 21.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 21.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 21.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 Freescale Semiconductor Chapter 20 Chapter 21 MC9S12C-Family / MC9S12GC-Family Rev 01.24 15 ...

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... A.4 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 A.5 NVM, Flash, and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 A.6 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 A.7 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 B.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 C.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 16 Appendix A Electrical Characteristics Appendix B Emulation Information Appendix C Package Information Appendix D Derivative Differences Appendix E Ordering Information MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

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... DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer) — MEBI (multiplexed expansion bus interface) available only in 80-pin package version • Wake-up interrupt inputs: — port bits available for wake up interrupt function with digital filtering Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24 17 ...

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... Real time interrupt — Clock monitor — Pierce or low current Colpitts oscillator — Phase-locked loop clock frequency multiplier — Limp home mode in absence of external clock — Low power 0.5MHz to 16MHz crystal oscillator reference clock 18 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

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... Special test mode (Freescale use only) — Special peripheral mode (Freescale use only) • Low power modes: — Stop mode — Pseudo stop mode — Wait mode Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) MC9S12C-Family / MC9S12GC-Family Rev 01.24 19 ...

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... PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PJ6 PJ7 RXD PS0 TXD PS1 PS2 PS3 RXCAN PM0 TXCAN PM1 MISO PM2 SS PM3 MOSI PM4 SCK PM5 V is bonded internally SSA for 52- and 48-Pin packages Freescale Semiconductor ...

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... External memory paging is not supported on this device 2. Not available on MC9S12GC Family devices Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-2 through Table 1-1. Device Register Map Overview Module Core (ports modes, inits, test) ...

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... Rev 01.24 1K Register Space PAGE MAP Mappable to any 2K Boundary 16K Fixed Flash EEPROM 0x003D 4K Bytes RAM Mappable to any 4K Boundary 16K Fixed Flash EEPROM 0x003E 16K Page Window 8 * 16K Flash EEPROM Pages PPAGE 16K Fixed Flash EEPROM 0x003F BDM (If Active) Freescale Semiconductor ...

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... The figure shows a useful map, which is not the map out of reset. After reset the map is: 0x0000–0x03FF: Register Space 0x0000–0x0FFF: 4K RAM (only 3K visible 0x0400–0x0FFF) Flash erase sector size is 1024 bytes Figure 1-3. MC9S12C96 and MC9S12GC96 User Configurable Memory Map Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0000 0x03FF 0x0000 0x3FFF ...

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... Rev 01.24 1K Register Space PAGE MAP Mappable to any 2K Boundary 16K Fixed Flash EEPROM 0x003D 4K Bytes RAM Mappable to any 4K Boundary 16K Fixed Flash EEPROM 0x003E 16K Page Window 4 * 16K Flash EEPROM Pages PPAGE 16K Fixed Flash EEPROM 0x003F BDM (If Active) Freescale Semiconductor ...

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... The flash page 0x003E is visible at 0x4000–0x7FFF in the memory map if ROMHM = 0. In the figure ROMHM = 1 removing page 0x003E from 0x4000–0x7FFF. Figure 1-5. MC9S12C32 and MC9S12GC32 User Configurable Memory Map Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0000 ...

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... VECTORS 0xFFFF SPECIAL SINGLE CHIP MC9S12C-Family / MC9S12GC-Family Rev 01.24 1K Register Space PAGE MAP Mappable to any 2K Boundary 1K Bytes RAM Mappable to any 2K Boundary 16K Page Window PPAGE 16K Fixed Flash EEPROM 0x003F BDM (If Active) Freescale Semiconductor ...

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... PEAR NOACCE Write: Read: 0x000B MODE Write: Read: 0x000C PUCR PUPKE Write: Read: 0x000D RDRIV Write: Read: 0x000E EBICTL Write: Read: 0x000F Reserved Write: Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Bit 7 Bit 6 Bit 5 Bit 4 Bit Bit Bit Bit ...

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... REG11 0 0 EE11 0 EXSTR1 EXSTR0 ROMHM Bit 3 Bit 2 Bit 1 ADR3 ADR2 ADR1 INT6 INT4 INT2 Bit 3 Bit 2 Bit Bit 3 Bit 2 Bit Bit 3 Bit 2 Bit LVDS LVIE Freescale Semiconductor Bit 0 RAMHAL 0 EEON ROMON 0 Bit 0 ADR0 INT0 Bit 0 0 Bit 0 0 Bit 0 LVIF ...

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... Write: Read: 0x0022 DBGTBH Write: Read: 0x0023 DBGTBL Write: Read: 0x0024 DBGCNT Write: Read: 0x0025 DBGCCX Write: Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Bit 7 Bit 6 Bit 5 Bit 4 ID15 ID14 ID13 ID12 ID7 ID6 ID5 ID4 Bit 7 Bit 6 Bit 5 ...

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... Rev 01.24 Bit 3 Bit 2 Bit 1 Bit Bit Bit 0 BKCEN TAGC RWCEN RWC RWAEN RWA RWBEN RWB EXTCMP Bit Bit 0 EXTCMP Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 PIX3 PIX2 PIX1 PIX0 Bit 3 Bit 2 Bit 1 Bit Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit Freescale Semiconductor ...

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... OC7D Write: Read: 0x0044 TCNT (hi) Write: Read: 0x0045 TCNT (lo) Write: Read: 0x0046 TSCR1 Write: Read: 0x0047 TTOV Write: Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Bit 7 Bit 6 Bit 5 Bit SYN5 SYN4 TOUT7 TOUT6 TOUT5 TOUT4 RTIF PORF LVRF ...

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... OM1 OL1 OM0 OL0 EDG5B EDG5A EDG4B EDG4A EDG1B EDG1A EDG0B EDG0A C3I C2I C1I C0I TCRE PR2 PR1 PR0 C3F C2F C1F C0F Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 8 Freescale Semiconductor 0 ...

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... Reserved Write: Read: 0x006E Reserved Write: Read: 0x006F Reserved Write: 0x0070–0x007F Reserved Address Name Read: 0x0070– Reserved 0x007F Write: Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Bit 7 Bit 6 Bit 5 Bit 4 Bit PAEN PAMOD PEDGE Bit 15 14 ...

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... Bit6 0 Bit15 Bit7 Bit6 0 Bit15 Bit7 Bit6 0 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Bit 3 Bit 2 Bit ETRIG ASCIE S1C FIFO FRZ1 PRS3 PRS2 PRS1 CC2 CC1 CCF3 CCF2 CCF1 Freescale Semiconductor Bit ASCIF FRZ0 PRS0 CA CC0 CCF0 0 Bit 0 0 BIT 0 Bit8 0 Bit8 0 Bit8 0 ...

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... Read: 0x00C8 SCIBDH Write: Read: 0x00C9 SCIBDL Write: Read: 0x00CA SCICR1 LOOPS Write: Read: 0x00CB SCICR2 Write: Read: 0x00CC SCISR1 Write: Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Bit 7 Bit 6 Bit 5 Bit 4 Bit15 Bit7 Bit6 0 0 Bit15 Bit7 Bit6 0 ...

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... MODFEN BIDIROE 0 SPPR2 SPPR1 SPPR0 SPIF 0 SPTEF MODF Bit7 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Bit 3 Bit 2 Bit 1 Bit 0 0 RAF BRK13 TXDIR Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit 0 CPOL CPHA SSOE LSBFE 0 SPISWAI SPC0 0 SPR2 SPR1 SPR0 Bit0 Freescale Semiconductor ...

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... PWMCNT5 Write: Read: $00F2 PWMPER0 Write: Read: $00F3 PWMPER1 Write: Read: $00F4 PWMPER2 Write: Read: $00F5 PWMPER3 Write: Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Bit 7 Bit 6 Bit 5 Bit PWME5 PWME4 0 0 PPOL5 PPOL4 0 0 PCLK5 PCLK4 0 PCKB2 ...

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... Bit 2 Bit (1) Bit 3 Bit 2 Bit 1 TIME WUPE SLPRQ 0 SLPAK WUPM BRP3 BRP2 BRP1 TSEG13 TSEG12 TSEG11 TSTAT1 TSTAT0 OVRIF OVRIE Freescale Semiconductor Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 Bit 0 0 Bit 0 INITRQ INITAK BRP0 TSEG10 RXF RXFIE ...

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... Not available on the MC9S12GC Family members. Those memory locations should not be accessed. Table 1-2. Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Extended ID Read: 0xXXX0 Standard ID Read: CANxRIDR0 Write: Extended ID Read: 0xXXX1 Standard ID Read: CANxRIDR1 Write: Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Bit 7 Bit 6 Bit 5 Bit ...

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... ID22 ID21 ID6 ID5 ID4 ID3 IDE=1 ID17 ID16 ID15 IDE=0 ID10 ID9 ID8 ID7 ID2 ID1 ID0 RTR DB3 DB2 DB1 DB0 DLC3 DLC2 DLC1 DLC0 PRIO3 PRIO2 PRIO1 PRIO0 TSR11 TSR10 TSR9 TSR8 TSR3 TSR2 TSR1 TSR0 Freescale Semiconductor ...

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... WOMS Write: Read: 0x024F Reserved Write: Read: 0x0250 PTM Write: Read: 0x0251 PTIM Write: Read: 0x0252 DDRM Write: Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Bit 7 Bit 6 Bit 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 PTT7 PTT6 PTT5 PTT4 PTIT7 PTIT6 ...

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... WOMM2 WOMM1 PTP3 PTP2 PTP1 PTIP3 PTIP2 PTIP1 DDRP3 DDRP2 DDRP1 RDRP3 RDRP2 RDRP1 PERP3 PERP2 PERP1 PPSP3 PPSP2 PPSP1 PIEP3 PIEP2 PIEP1 PIFP3 PIFP2 PIFP1 Freescale Semiconductor Bit 0 RDRM0 PERM0 PPSM0 WOMM0 0 PTP0 PTIP0 DDRP0 RDRP0 PERP0 PPSS0 PIEP0 PIFP0 ...

Page 43

... Reserved 0x027F Write: 0x0280–0x03FF Reserved Space Address Name Read: 0x0280– Reserved 0x2FF Write: Read: 0x0300 Unimplemented –0x03FF Write: Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Bit 7 Bit 6 Bit 5 Bit 4 0 DDRJ7 DDRJ7 0 RDRJ7 RDRJ6 0 PERJ7 PERJ6 0 PPSJ7 ...

Page 44

... Table 1-4. Memory Size Registers Register Name MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Table 1-3 shows the assigned (1) Part ID $3300 $3302 $3311 $3302 $3302 $3311 $3102 $3102 $3103 $3103 Value $00 $80 $00 $80 $01 $C0 $01 $C0 $01 $C0 Freescale Semiconductor ...

Page 45

... MODRR since this is intended to support PWM channel availability in low pin count packages. Note that when mapping PWM channels to Port 80QFP option, the associated PWM channels are then mapped to both Port P and Port T Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1 ...

Page 46

... IOC6/PT6 11 IOC7/PT7 12 MODC/BKGD 13 PB4 * Signals shown in Bold italic are not available on the 48-pin package Figure 1-8. Pin Assignments in 52-Pin LQFP 46 MC9S12C-Family / MC9S12GC-Family MC9S12C-Family / MC9S12GC-Family Rev 01. DDA 37 PAD07/AN07 PAD06/AN06 36 PAD05/AN05 35 PAD04/AN04 34 PAD03/AN03 33 PAD02/AN02 32 PAD01/AN01 31 PAD00/AN00 30 29 PA2 28 PA1 27 PA0 Freescale Semiconductor ...

Page 47

... PW1/IOC1/PT1 2 PW2/IOC2/PT2 3 PW3/IOC3/PT3 DD1 V 6 SS1 IOC4/PT4 7 8 IOC5/PT5 9 IOC6/PT6 10 IOC7/PT7 11 MODC/BKGD 12 PB4 Figure 1-9. Pin Assignments in 48-Pin LQFP Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) MC9S12C-Family / MC9S12GC-Family MC9S12C-Family / MC9S12GC-Family Rev 01. DDA 34 PAD07/AN07 PAD06/AN06 33 PAD05/AN05 32 PAD04/AN04 31 PAD03/AN03 30 PAD02/AN02 29 PAD01/AN01 ...

Page 48

... PERP/ Port P I/O pins, keypad wake-up, and ROMON V Disabled DDX PPSP enable. PERP/ Port P I/O pin, keypad wake-up, PW5 output V Disabled DDX PPSP PERP/ Port P I/O pin, keypad wake-up, PWM output V Disabled DDX PPSP MC9S12C-Family / MC9S12GC-Family Rev 01.24 Description Freescale Semiconductor ...

Page 49

... Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port J[7:6], PortS[3:2] (52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port J[7:6], PortS[3:2] Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Table 1-5. Signal Properties (continued) Internal Pull ...

Page 50

... It is also used as a MCU operating mode select pin at the rising edge during reset, when the state of this pin is latched to the MODC bit all applications. SS XFC R 0 MCU DDPLL Figure 1-10. PLL Loop Filter Connections MC9S12C-Family / MC9S12GC-Family Rev 01. DDPLL Freescale Semiconductor ...

Page 51

... Figure 1-11. Colpitts Oscillator Connections (PE7 = 1) EXTAL MCU XTAL 1. RS can be zero (shorted) when used with higher frequency crystals, refer to manufacturer’s data. Figure 1-12. Pierce Oscillator Connections (PE7 = 0) Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1 CDC C 1 Ceramic Resonator ...

Page 52

... This pin is also used as TAGLO in special expanded modes and is multiplexed with the LSTRB function. This pin is not available in the 48- / 52-pin package versions. 52 CMOS Compatible EXTAL External Oscillator (V Level) DDPLL MCU XTAL Not Connected MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 53

... PP6 is a general purpose input or output pin, shared with the keypad interrupt function. When configured as an input, it can generate interrupts causing the MCU to exit stop or wait mode. This pin is not available in the 48- / 52-pin package versions. During MCU expanded modes of operation, this pin is used to enable Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) MC9S12C-Family / MC9S12GC-Family Rev 01 ...

Page 54

... PM1 is a general purpose input or output pin and the transmit pin, TXCAN, of the CAN module if available. 1.3.4.26 PM0 / RXCAN — Port M I/O Pin 0 PM0 is a general purpose input or output pin and the receive pin, RXCAN, of the CAN module if available. 54 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 55

... DD1 DD2 SS1 Power is supplied to the MCU through V regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off tied to ground. Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128 — Internal Logic Power Pins SS2 and V . This 2.5V supply is derived from the internal voltage ...

Page 56

... MCU as possible. Bypass requirements depend on MCU pin load. 56 — Power Supply Pins for PLL Description /V voltages and bypass the internal voltage regulator and V DD2 SS2 is bonded NOTE MC9S12C-Family / MC9S12GC-Family Rev 01.24 are not available. . SSA Freescale Semiconductor ...

Page 57

... ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal. Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Core Clock ...

Page 58

... Peripheral; BDM allowed but bus operations would cause bus X 1 conflicts (must not be used Normal Expanded Wide, BDM allowed 1 1 Table 1-8. Clock Selection Based on PE7 Description Colpitts Oscillator selected Pierce Oscillator/external clock selected MC9S12C-Family / MC9S12GC-Family Rev 01.24 Mode Description Freescale Semiconductor ...

Page 59

... Other peripherals are turned off. This mode consumes more current than the full stop mode, but the wake up time from this mode is significantly shorter. Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) MC9S12C-Family / MC9S12GC-Family Rev 01 ...

Page 60

... COP rate select — None — None — None — INTCR (IRQEN) 0x00F2 CRGINT (RTIE) 0x00F0 TIE (C0I) 0x00EE TIE (C1I) 0x00EC TIE (C2I) 0x00EA TIE (C3I) 0x00E8 TIE (C4I) 0x00E6 TIE (C5I) 0x00E4 TIE (C6I) 0x00E2 TIE (C7I) 0x00E0 Freescale Semiconductor ...

Page 61

... PWM Emergency Shutdown 0xFF8A, 0xFF8B 0xFF80 to 0xFF89 1. Not available on MC9S12GC Family members Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) CCR Mask I bit I bit I bit SPI I bit SCI ...

Page 62

... CRG module 1 RESET pin 1 VREG module 2 CRG module 3 CRG module footnotes for locations of the memories depending on the operating mode NOTE Table 1-5 for affected pins. MC9S12C-Family / MC9S12GC-Family Rev 01.24 Vector 0xFFFE, 0xFFFF 0xFFFE, 0xFFFF 0xFFFE, 0xFFFF 0xFFFC, 0xFFFD 0xFFFA, 0xFFFB Freescale Semiconductor ...

Page 63

... To prevent unnecessary current flow in production package options, the states of DDRK and PUPKE should not be changed by software. Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) PAGE Visible with PPAGE Contents $01,$03,$05,$07,$09......$35,$37,$39,$3B,$3D,$3F ...

Page 64

... V SS2 and V of the 2.5V domain are bonded out & DD1 SS1 DD2 SS2 NOTE pad is bonded internally to the V RL MC9S12C-Family / MC9S12GC-Family Rev 01.24 DDR and V are connected together DD1 DD2 to ground then the DDR pin. SSA Freescale Semiconductor . ...

Page 65

... QFP only) DD2 C9 C10 C11 R1 Pierce Mode Select Pullup 48LQFP and 52LQFP package versions DD1 Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) pin. SSR . SSR /V DDA SSA Purpose V filter capacitor Ceramic X7R DD1 V filter capacitor X7R/tantalum DDR V fi ...

Page 66

... Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-15. Recommended PCB Layout (48 LQFP) Colpitts Oscillator 66 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 67

... Figure 1-16. Recommended PCB Layout (52 LQFP) Colpitts Oscillator Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) MC9S12C-Family / MC9S12GC-Family Rev 01.24 67 ...

Page 68

... Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-17. Recommended PCB Layout (80 QFP) Colpitts Oscillator 68 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 69

... Figure 1-18. Recommended PCB Layout for 48 LQFP Pierce Oscillator Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) MC9S12C-Family / MC9S12GC-Family Rev 01.24 69 ...

Page 70

... Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-19. Recommended PCB Layout for 52 LQFP Pierce Oscillator 70 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 71

... Figure 1-20. Recommended PCB Layout for 80QFP Pierce Oscillator Freescale Semiconductor Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) MC9S12C-Family / MC9S12GC-Family Rev 01.24 71 ...

Page 72

... Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 72 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 73

... Input with selectable pull-up or pull-down device Optional features: • Open drain for wired-OR connections • Interrupt inputs with glitch filtering Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24 73 ...

Page 74

... IOC6 IOC7 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 RXD TXD RXCAN TXCAN MISO MOSI SCK SS XIRQ IRQ R/W ECLK Freescale Semiconductor PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PS0 PS1 PS2 PS3 ...

Page 75

... PWM channels to Port 80QFP option, the associated PWM channels are then mapped to both Port P and Port T. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description MC9S12C-Family / MC9S12GC-Family Rev 01.24 75 ...

Page 76

... MSCAN receive pin PWM outputs General purpose I/O with interrupt ROMON input signal General purpose I/O with interrupt ATD analog inputs General purpose I/O Refer to MEBI Block Guide. Refer to MEBI Block Guide. MC9S12C-Family / MC9S12GC-Family Rev 01.24 Pin Function after Reset GPIO Freescale Semiconductor ...

Page 77

... RDRT RDRT7 W R 0x0004 PERT PERT7 W R 0x0005 PPST PPST7 W Figure 2-2. Quick Reference to PIM Registers (Sheet Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description Description Refer to MEBI Block Guide PTT6 PTT5 PTT4 IOC6 IOC5 IOC4 PWM4 PTIT6 PTIT5 ...

Page 78

... PTIM3 PTIM2 PTIM1 PTIM0 DDRM3 DDRM2 DDRM1 DDRM0 RDRM3 RDRM2 RDRM1 RDRM0 PERM3 PERM2 PERM1 PERM0 PPSM3 PPSM2 PPSM1 PPSM0 WOMM3 WOMM2 WOMM1 WOMM0 PTP3 PTP2 PTP1 PTP0 PWM3 PWM2 PWM1 PWM0 PTIP3 PTIP2 PTIP1 PTIP0 Freescale Semiconductor Bit 0 0 RXD 0 0 ...

Page 79

... W R 0x0034 PERAD PERAD7 W R 0x0035 PPSAD PPSAD7 W R 0x0036– Reserved 0x003F W Figure 2-2. Quick Reference to PIM Registers (Sheet Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description DDRP6 DDRP5 DDRP4 RDRP6 RDRP5 RDRP4 PERP6 PERP5 PERP4 PPSP6 PPSP5 PPSP4 ...

Page 80

... Disabled Pull up Disabled Pull down Disabled Disabled Falling edge Disabled Rising edge Pull up Falling edge Pull down rising edge Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Falling edge Disabled Rising edge Disabled Falling edge Disabled Rising edge Freescale Semiconductor ...

Page 81

... TIMEN[x] means that the timer is enabled (TSCR1[7]), the related channel is configured for output compare function (TIOS[x] or special output on a timer overflow event — configurable in TTOV[x]) and the timer output is routed to the port pin (TCTL1/TCTL2). Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 5 4 ...

Page 82

... PTIT5 PTIT4 PTIT3 — — — Figure 2-4. Port T Input Register (PTIT) Table 2-4. PTIT Field Descriptions Description DDRT5 DDRT4 DDRT3 Table 2-5. DDRT Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. PTIT2 PTIT1 PTIT0 — — — DDRT2 DDRT1 DDRT0 Freescale Semiconductor ...

Page 83

... Pull Device Enable — This register configures whether a pull- pull-down device is activated, if the port PERT[7:0] is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled. 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description ...

Page 84

... MODRR[4:0] 0 Associated pin is connected to TIM module 1 Associated pin is connected to PWM module PPST5 PPST4 PPST3 Table 2-8. PPST Field Descriptions Description MODRR4 MODRR3 — NOTE Table 2-9. MODRR Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. PPST2 PPST1 PPST0 MODRR2 MODRR1 MODRR0 Freescale Semiconductor ...

Page 85

... Write: Never, writes to this register have no effect. Field 3–0 Port S Input Register — This register always reads back the status of the associated pins. This also can be PTIS[3:0] used to detect overload or short circuit conditions on output pins. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description ...

Page 86

... Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take bus cycles until the correct value is read on PTS or PTIS registers, when changing the DDRS register DDRS3 Table 2-11. DDRS Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. DDRS2 DDRS1 DDRS0 Freescale Semiconductor ...

Page 87

... PERS[3:0] is used as input or as output in wired-or (open drain) mode. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled. 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description ...

Page 88

... A logic level of “1” is not driven. This bit has no influence on pins used as inputs. 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs PPSS3 Table 2-14. PPSS Field Descriptions Description WOMS3 Table 2-15. WOMS Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. PPSS2 PPSS1 PPSS0 WOMS2 WOMS1 WOMS0 Freescale Semiconductor ...

Page 89

... Write: Never, writes to this register have no effect. Field 5–0 Port M Input Register — This register always reads back the status of the associated pins. This also can be PTIM[5:0] used to detect overload or short circuit conditions on output pins. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description PTM5 ...

Page 90

... Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take bus cycles until the correct value is read on PTM or PTIM registers, when changing the DDRM register DDRM5 DDRM4 DDRM3 Table 2-17. DDRM Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. DDRM2 DDRM1 DDRM0 Freescale Semiconductor ...

Page 91

... This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled. 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 5 4 ...

Page 92

... A logic level of “1” is not driven. This bit has no influence on pins used as inputs. 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs PPSM5 PPSM4 PPSM3 Table 2-20. PPSM Field Descriptions Description WOMM5 WOMM4 WOMM3 Table 2-21. WOMM Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. PPSM2 PPSM1 PPSM0 WOMM2 WOMM1 WOMM0 Freescale Semiconductor ...

Page 93

... Unimplemented or Reserved Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can be also used to detect overload or short circuit conditions on output pins. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description ...

Page 94

... Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength DDRP5 DDRP4 DDRP3 Table 2-22. DDRP Field Descriptions Description RDRP5 RDRP4 RDRP3 Table 2-23. RDRP Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. DDRP2 DDRP1 DDRP0 RDRP2 RDRP1 RDRP0 Freescale Semiconductor ...

Page 95

... Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-down device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 5 ...

Page 96

... Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated flag PIEP5 PIEP4 PIEP3 Table 2-26. PIEP Field Descriptions Description PIFP5 PIFP4 PIFP3 Table 2-27. PIFP Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. PIEP2 PIEP1 PIEP0 PIFP2 PIFP1 PIFP0 Freescale Semiconductor ...

Page 97

... Reset Unimplemented or Reserved Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can be used to detect overload or short circuit conditions on output pins. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description — ...

Page 98

... Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength — — — Table 2-28. DDRJ Field Descriptions Description — — — Table 2-29. RDRJ Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. — — — — — — Freescale Semiconductor ...

Page 99

... Rising edge on the associated port J pin sets the associated flag bit in the PIFJ register. A pull-down device is connected to the associated port J pin, if enabled by the associated bit in register PERJ and if the port is used as input. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 5 ...

Page 100

... Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated flag. 100 — — — Table 2-32. PIEJ Field Descriptions Description — — — Table 2-33. PIFJ Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. — — — — — — Freescale Semiconductor ...

Page 101

... Unimplemented or Reserved Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can be used to detect overload or short circuit conditions on output pins. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 5 4 PTAD5 ...

Page 102

... Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. 102 DDRAD5 DDRAD4 DDRAD3 Table 2-34. DDRAD Field Descriptions Description RDRAD5 RDRAD4 RDRAD3 Table 2-35. RDRAD Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. DDRAD2 DDRAD1 DDRAD0 RDRAD2 RDRAD1 RDRAD0 Freescale Semiconductor ...

Page 103

... A pull-up device is connected to the associated port AD pin, if enabled by the associated bit in register PERAD and if the port is used as input pull-down device is connected to the associated port AD pin, if enabled by the associated bit in register PERAD and if the port is used as input. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 5 4 ...

Page 104

... This register defines whether the pin is used as an input or an output peripheral module controls the pin the contents of the data direction register is ignored 104 2-46). PTI DDR 1 Data Out Output Enable Module Enable (Figure MC9S12C-Family / MC9S12GC-Family Rev 01.24 PAD (Figure 2-46). 2-46). Freescale Semiconductor ...

Page 105

... DDRD[n] must be set NOTE: To use PORTAD[n], located in the ATD as an input port register, DDRD[n] must be cleared and ATDDIEN[n] must be set. Please refer to ATD Block Guide for details. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description MC9S12C-Family / MC9S12GC-Family Rev 01 ...

Page 106

... Bus clocks pign 3 < t < 4 Bus clocks 3.2 < t pulse t >= 4 Bus clocks pval t pulse Figure 2-48. Pulse Illustration MC9S12C-Family / MC9S12GC-Family Rev 01.24 (Figure 2-47 (1) STOP Mode Value Unit µs t <= 3.2 pign µs < 10 pulse µs t >= 10 pval Freescale Semiconductor and ...

Page 107

... The reset values of all registers are given in 2.5.1 Reset Initialization All registers including the data registers get set/reset asynchronously. properties after reset initialization. Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description Section 2.3.2, “Register MC9S12C-Family / MC9S12GC-Family Rev 01.24 Descriptions”. ...

Page 108

... Refer to MEBI Block Guide for details. Refer to BDM Block Guide for details. Interrupt Flag Local Enable PIFP[7:0] PIEP[7:0] PIFJ[7:6] PIEJ[7:6] NOTE MC9S12C-Family / MC9S12GC-Family Rev 01.24 Wired-OR Mode Interrupt n/a n/a Disabled n/a Disabled n/a n/a Disabled n/a Disabled Global (CCR) Mask I Bit I Bit Freescale Semiconductor ...

Page 109

... The MMC is the sub-module which controls memory map assignment and selection of internal resources and external space. Internal buses between the core and memories and between the core and peripherals is controlled in this module. The memory expansion is generated in this module. Freescale Semiconductor Figure 3-1. ...

Page 110

... Initialization of Internal Registers Position Register (INITRG) 0x0012 Initialization of Internal EEPROM Position Register (INITEE) 0x0013 Miscellaneous System Control Register (MISC) 0x0014 Reserved . . 110 Table 3-1. MMC Memory Map Register . . MC9S12C-Family / MC9S12GC-Family Rev 01.24 Figure 3-2. Detailed Access R/W R/W R/W R/W — — Freescale Semiconductor ...

Page 111

... Memory Size Register 0 (MEMSIZ0) 0x001D Memory Size Register 1 (MEMSIZ1 0x0030 Program Page Index Register (PPAGE) 0x0031 Reserved Freescale Semiconductor Chapter 3 Module Mapping Control (MMCV4) Block Description Table 3-1. MMC Memory Map (continued) Register . . . . MC9S12C-Family / MC9S12GC-Family Rev 01.24 Access — ...

Page 112

... EE13 EE12 EEP_SW1 EEP_SW0 PIX5 PIX4 Unimplemented Figure 3-2. MMC Register Summary MC9S12C-Family / MC9S12GC-Family Rev 01. RAM11 0 0 REG11 0 0 EE11 EXSTR1 EXSTR0 ROMHM RAM_SW2 RAM_SW1 RAM_SW0 0 0 PAG_SW1 PAG_SW0 PIX3 PIX2 PIX1 Freescale Semiconductor Bit 0 RAMHAL 0 EEON ROMON Bit 0 Bit 0 PIX0 0 ...

Page 113

... RAM High-Align — RAMHAL specifies the alignment of the internal RAM array. RAMHAL 0 Aligns the RAM to the lowest address (0x0000) of the mappable space 1 Aligns the RAM to the higher address (0xFFFF) of the mappable space Freescale Semiconductor Chapter 3 Module Mapping Control (MMCV4) Block Description 5 4 ...

Page 114

... REG[14:11] INITRG determine the upper five bits of the base address for the system’s internal registers (i.e., the minimum base address is 0x0000 and the maximum is 0x7FFF). 114 REG13 REG12 REG11 Table 3-3. INITRG Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. Freescale Semiconductor ...

Page 115

... Enable EEPROM — This bit is used to enable the EEPROM memory in the memory map. EEON 0 Disables the EEPROM from the memory map. 1 Enables the EEPROM in the memory map at the address selected by EE[15:11]. Freescale Semiconductor Chapter 3 Module Mapping Control (MMCV4) Block Description EE13 ...

Page 116

... This bit is used to enable the FLASH EEPROM or ROM memory in the memory map. 0 Disables the FLASH EEPROM or ROM from the memory map. 1 Enables the FLASH EEPROM or ROM in the memory map. 116 EXSTR1 NOTE Table 3-5. INITEE Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. EXSTR0 ROMHM ROMON Freescale Semiconductor 0 1 — ...

Page 117

... Unimplemented or Reserved Figure 3-8. Reserved Test Register 1 (MTST1) Read: Anytime Write: No effect — this register location is used for internal test purposes. Freescale Semiconductor Chapter 3 Module Mapping Control (MMCV4) Block Description Table 3-6. External Stretch Bit Definition Stretch Bit EXSTR0 Number of E Clocks Stretched ...

Page 118

... Table 3-9. Allocated RAM Memory Space RAM Mappable Region 2K bytes 4K bytes (2) 8K bytes MC9S12C-Family / MC9S12GC-Family Rev 01. RAM_SW2 RAM_SW1 — — 0K byte 2K bytes 4K bytes 8K bytes INITRM RAM Reset Bits Used Base Address RAM[15:11] 0x0800 RAM[15:12] 0x0000 RAM[15:13] 0x0800 Freescale Semiconductor 0 RAM_SW0 — (1) ...

Page 119

... The MEMSIZ1 register reflects the state of the FLASH or ROM physical memory space and paging switches at the core boundary which are configured at system integration. This register allows read visibility to the state of these switches. Freescale Semiconductor Chapter 3 Module Mapping Control (MMCV4) Block Description RAM ...

Page 120

... Section 3.3.2.8, “Memory Size Register 1 Off-Chip Space 876K bytes 768K bytes 512K bytes 0K byte NOTE MC9S12C-Family / MC9S12GC-Family Rev 01.24 Allocated FLASH or ROM Space 0K byte 16K bytes (1) 48K bytes (1) 64K bytes On-Chip Space 128K bytes 256K bytes 512K bytes 1M byte Freescale Semiconductor ...

Page 121

... Field 5:0 Program Page Index Bits 5:0 — These page index bits are used to select which of the 64 FLASH or ROM PIX[5:0] array pages accessed in the program page window as shown in Freescale Semiconductor Chapter 3 Module Mapping Control (MMCV4) Block Description PIX5 ...

Page 122

... Normally, I/O addresses, control registers, 122 PIX3 PIX2 PIX1 PIX0 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Program Space Selected 16K page 0 16K page 1 16K page 2 16K page 16K page 60 16K page 61 16K page 62 16K page 63 Freescale Semiconductor ...

Page 123

... XCS. This signal is active only when the ECS signal described above is not active and when the system is addressing the external address space. Accesses to Freescale Semiconductor Chapter 3 Module Mapping Control (MMCV4) Block Description Table 3-15. Select Signal Priority Address Space BDM (internal to core) fi ...

Page 124

... NOTE Table 3-17 applies only to the allocated MC9S12C-Family / MC9S12GC-Family Rev 01.24 Table 3-12 but is repeated here for On-Chip Space 128K bytes 256K bytes 512K bytes 1M byte Page Window Access External Internal External Internal External Internal External Internal Freescale Semiconductor ...

Page 125

... The RTC instruction terminates subroutines invoked by a CALL instruction. RTC unstacks the PPAGE value and the return address and refills the queue. Execution resumes with the next instruction after the CALL. Freescale Semiconductor Chapter 3 Module Mapping Control (MMCV4) Block Description MC9S12C-Family / MC9S12GC-Family Rev 01 ...

Page 126

... N/A N/A Page Window Access ROMHM N/A N/A N/A N/A N/A N/A N/A N/A MC9S12C-Family / MC9S12GC-Family Rev 01.24 Section 3.3.2.4, “Miscellaneous Table 3-19, Table 3-20, and Table 3- ECS XAB19:14 1 0x3D 1 0x3E 0 PIX[5:0] 0 0x3F ECS XAB19:14 1 0x3D 1 0x3E 1 PIX[5:0] 0 0x3F Freescale Semiconductor ...

Page 127

... Table 3-21. 64K Byte Physical FLASH/ROM Allocated Address Space 0x0000–0x3FFF 0x4000–0x7FFF 0x8000–0xBFFF 0xC000–0xFFFF Freescale Semiconductor Chapter 3 Module Mapping Control (MMCV4) Block Description Page Window Access ROMHM N/A N/A N/A 0 N/A 1 ...

Page 128

... Figure 3-12. Memory Paging Example: 1M Byte On-Chip FLASH/ROM, 64K Allocation 128 Figure 3-12. ONE 16K FLASH/ROM PAGE ACCESSIBLE AT A TIME (SELECTED BY PPAGE = These 16K FLASH/ROM pages accessible from 0x0000 to 0x7FFF if selected by the ROMHM bit in the MISC register. MC9S12C-Family / MC9S12GC-Family Rev 01. Freescale Semiconductor ...

Page 129

... Control register to configure external clock behavior • Control register to configure IRQ pin operation • Logic to capture and synchronize external interrupt pin inputs Freescale Semiconductor Figure 4-1, the signals on the right hand side represent pins MC9S12C-Family / MC9S12GC-Family Rev 01.24 129 ...

Page 130

... DATA ECLK CTL PIPE CTL IRQ CTL TAG CTL mode Figure 4-1. MEBI Block Diagram MC9S12C-Family / MC9S12GC-Family Rev 01.24 PK[7:0]/ECS/XCS/X[19:14] PA[7:0]/A[15:8]/ D[15:8]/D[7:0] PB[7:0]/A[7:0]/ D[7:0] PE[7:2]/NOACC/ IPIPE1/MODB/CLKTO IPIPE0/MODA/ ECLK/ LSTRB/TAGLO R/W PE1/IRQ PE0/XIRQ BKGD/MODC/TAGHI BKGD Freescale Semiconductor ...

Page 131

... Special peripheral mode This mode is intended for Freescale Semiconductor factory testing of the system. The CPU is inactive and an external (tester) bus master drives address, data, and bus control signals. 4.2 External Signal Description In typical implementations, the MEBI sub-block of the core interfaces directly with external system pins ...

Page 132

... The enable for this function is in the clock module. At the rising edge on RESET, the state of this pin is registered into the MODA bit to set the mode. General-purpose I/O pin, see PORTE and DDRE registers. Instruction pipe status bit 0, enabled by PIPOE bit in PEAR. MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 133

... A summary of the registers associated with the MEBI sub-block is shown in descriptions of the registers and bits are given in the subsections that follow. On most chips the registers are mappable. Therefore, the upper bits may not be all 0s as shown in the table and descriptions. Freescale Semiconductor Chapter 4 Multiplexed External Bus Interface (MEBIV3) Description General-purpose I/O pin, see PORTE and DDRE registers ...

Page 134

... MC9S12C-Family / MC9S12GC-Family Rev 01.24 Access R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R PA3 PA2 PA1 AB/DB11 AB/DB10 AB/DB9 AB11 and AB10 and AB9 and DB11/DB3 DB10/DB2 DB9/DB1 Freescale Semiconductor 0 Bit 0 0 PA0 AB/DB8 AB8 and DB8/DB0 ...

Page 135

... This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. To ensure that you read the value present on the PORTB pins, always wait at least one cycle after writing to the DDRB register before reading from the PORTB register. Freescale Semiconductor Chapter 4 Multiplexed External Bus Interface (MEBIV3) NOTE 6 5 ...

Page 136

... It is reset to 0x00 so the DDR does not override the three-state control signals. Field 7:0 Data Direction Port A DDRA 0 Configure the corresponding I/O pin as an input 1 Configure the corresponding I/O pin as an output 136 Table 4-3. DDRA Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. Bit Freescale Semiconductor ...

Page 137

... It is reset to 0x00 so the DDR does not override the three-state control signals. Field 7:0 Data Direction Port B DDRB 0 Configure the corresponding I/O pin as an input 1 Configure the corresponding I/O pin as an output Freescale Semiconductor Chapter 4 Multiplexed External Bus Interface (MEBIV3 ...

Page 138

... Starting address location affected by INITRG register setting Reset Unimplemented or Reserved Module Base + 0x0007 Starting address location affected by INITRG register setting Reset Unimplemented or Reserved 138 Figure 4-6. Reserved Register Figure 4-7. Reserved Register Figure 4-8. Reserved Register Figure 4-9. Reserved Register MC9S12C-Family / MC9S12GC-Family Rev 01. Freescale Semiconductor ...

Page 139

... It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from being inputs to outputs, the data may have extra transitions during the write best to initialize PORTE before enabling as outputs. Freescale Semiconductor Chapter 4 Multiplexed External Bus Interface (MEBIV3 ...

Page 140

... Note unwise to write PORTE and DDRE as a word access. If you are changing port E pins from inputs to outputs, the data may have extra transitions during the write best to initialize PORTE before enabling as outputs. 140 NOTE Table 4-5. DDRE Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. Bit Freescale Semiconductor ...

Page 141

... In special test and emulation modes, IPIPE1, IPIPE0, E, LSTRB, and R/W are configured out of reset as bus control signals. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. Freescale Semiconductor Chapter 4 Multiplexed External Bus Interface (MEBIV3 ...

Page 142

... This bit has no effect in single-chip or special peripheral modes. Note: R/W is used for external writes. After reset in normal expanded mode, R/W is disabled to provide an extra I/O pin. If R/W is needed it should be enabled before any external writes. 142 Table 4-6. PEAR Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 143

... In special peripheral mode, this register is not accessible but it is reset as shown to system configuration features. Changes to bits in the MODE register are delayed one cycle after the write. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. Freescale Semiconductor Chapter 4 Multiplexed External Bus Interface (MEBIV3 ...

Page 144

... Removing the registers from the map allows the user to emulate the function of these registers externally. In single-chip modes, PORTE and DDRE are always in the map regardless of the state of this bit. 144 Table 4-7. MODE Field Descriptions Description 4-16. MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 145

... The polarity of these pull resistors is determined by chip integration. Please refer to the device overview chapter to determine the polarity of these resistors. Freescale Semiconductor Chapter 4 Multiplexed External Bus Interface (MEBIV3) Mode ...

Page 146

... This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. 146 NOTE Table 4-9. PUCR Field Descriptions Description RDPE MC9S12C-Family / MC9S12GC-Family Rev 01. RDPB RDPA Freescale Semiconductor ...

Page 147

... Special: write anytime 0 E never stretches (always free running stretches high during stretched external accesses and remains low during non-visible internal accesses. This bit has no effect in single-chip modes. Freescale Semiconductor Chapter 4 Multiplexed External Bus Interface (MEBIV3) Table 4-10. RDRIV Field Descriptions Description ...

Page 148

... External IRQ pin is disconnected from interrupt logic. 1 External IRQ pin is connected to interrupt logic. Note: When IRQEN = 0, the edge detect latch is disabled. 148 Figure 4-17. Reserved Register Figure 4-18. IRQ Control Register (IRQCR) Table 4-12. IRQCR Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01. Freescale Semiconductor ...

Page 149

... They can be viewed as expanded addresses XAB19–XAB14 of the 20-bit address used to access up to1M byte internal FLASH/ROM or external memory array. Alternatively, these bits can be used for general-purpose I/O depending upon the state of the EMK bit in the MODE register. Freescale Semiconductor 5 4 ...

Page 150

... Table 4-14. EBICTL Field Descriptions Description AB0 R/W Type of Access 0 1 8-bit read of an even address 1 1 8-bit read of an odd address 0 0 8-bit write of an even address 1 0 8-bit write of an odd address MC9S12C-Family / MC9S12GC-Family Rev 01. Bit Table 4-15. Freescale Semiconductor ...

Page 151

... MODC MODB Freescale Semiconductor Chapter 4 Multiplexed External Bus Interface (MEBIV3) AB0 R 16-bit read of an even address 1 1 16-bit read of an odd address (low/high data swapped 16-bit write to an even address 1 0 16-bit write to an odd address (low/high data swapped) NOTE Table 4-16 ...

Page 152

... Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system. 152 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 153

... LSTRB would also be needed to fully understand system activity. Development systems where pipe status signals are monitored would typically use special expanded wide mode or occasionally special expanded narrow mode. Freescale Semiconductor Chapter 4 Multiplexed External Bus Interface (MEBIV3) MC9S12C-Family / MC9S12GC-Family Rev 01 ...

Page 154

... I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted. The main difference between special modes and normal modes is that some of the bus control and system control signals cannot be written in emulation modes. 154 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 155

... MCU acts was a peripheral under control of an external CPU. This allows faster testing of on-chip memory and peripherals than previous testing methods. Since the mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a different Freescale Semiconductor Chapter 4 Multiplexed External Bus Interface (MEBIV3) MC9S12C-Family / MC9S12GC-Family Rev 01 ...

Page 156

... Expanded bus modes will increase power consumption. 4.4.5.2 Operation in Wait Mode The MEBI does not contain any options for reducing power in wait mode. 4.4.5.3 Operation in Stop Mode The MEBI will cease to function after execution of a CPU STOP instruction. 156 NOTE MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 157

... This section describes the functionality of the interrupt (INT) sub-block of the S12 core platform. A block diagram of the interrupt sub-block is shown in WRITE DATA BUS INTERRUPTS XMASK IMASK RESET FLAGS VECTOR REQUEST Freescale Semiconductor Figure 5-1. INT HPRIO (OPTIONAL) HIGHEST PRIORITY I-INTERRUPT INTERRUPT INPUT REGISTERS ...

Page 158

... Interrupts may be tested in special modes through the use of the interrupt test registers. • Emulation modes The INT operates the same in emulation modes as in normal modes. • Low power modes See Section 5.4.1, “Low-Power 158 Modes,” for details MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 159

... Starting address location affected by INITRG register setting Reset Unimplemented or Reserved Figure 5-2. Interrupt Test Control Register (ITCR) Read: See individual bit descriptions Write: See individual bit descriptions Freescale Semiconductor Table 5-1. INT Memory Map Use WRTINT ADR3 MC9S12C-Family / MC9S12GC-Family Rev 01.24 ...

Page 160

... TEST registers (WRTINT = 1). Reads will always return 0s in normal modes. Write: Only in special modes and with WRTINT = 1 and CCR I mask = 1. 160 Table 5-2. ITCR Field Descriptions Description INTA INT8 INT6 MC9S12C-Family / MC9S12GC-Family Rev 01. INT4 INT2 INT0 Freescale Semiconductor ...

Page 161

... The interrupt sub-block processes all exception requests made by the CPU. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below. Freescale Semiconductor Table 5-3. ITEST Field Descriptions Description ...

Page 162

... HPRIO vector to the priority decoder if the highest priority I interrupt is active. RTI replaces the promoted interrupt source. 162 Figure 5-1, the INT contains a register block to provide interrupt status Register,” and Section 5.3.2.2, “Interrupt Test MC9S12C-Family / MC9S12GC-Family Rev 01.24 Registers,” Freescale Semiconductor ...

Page 163

... Vector Address 0xFFFE–0xFFFF 0xFFFC–0xFFFD 0xFFFA–0xFFFB 0xFFF8–0xFFF9 0xFFF6–0xFFF7 0xFFF4–0xFFF5 0xFFF2–0xFFF3 0xFFF0–0xFF00 Freescale Semiconductor NOTE Source System reset Crystal monitor reset COP reset Unimplemented opcode trap Software interrupt instruction (SWI) or BDM vector request XIRQ signal IRQ signal Device-specifi ...

Page 164

... Chapter 5 Interrupt (INTV1) Block Description 164 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 165

... BDMV4: SYNC command to determine communication rate • BDMV4: GO_UNTIL command • BDMV4: Hardware handshake protocol to increase the performance of the serial communication • Active out of reset in special single-chip mode Freescale Semiconductor Figure 6-1. 16-BIT SHIFT REGISTER BUS INTERFACE INSTRUCTION DECODE AND AND EXECUTION ...

Page 166

... General operation of the BDM is available and operates the same as in normal modes. 6.1.2.2 Secure Mode Operation If the part is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents access to FLASH or EEPROM other than allowing erasure. 166 NOTE MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 167

... This pin is used to tag the low byte of an instruction. When instruction tagging is on and low strobe is enabled, a logic 0 at the falling edge of the external clock (ECLK) tags the low half of the instruction word being read into the instruction queue. Freescale Semiconductor Chapter 6 Background Debug Module (BDMV4) Block Description NOTE MC9S12C-Family / MC9S12GC-Family Rev 01 ...

Page 168

... BDM CCR Holding Register (BDMCCR) 0xFF07 BDM Internal Register Position (BDMINR) 0xFF08– Reserved 0xFF0B 168 Figure Table 6-1. INT Memory Map Use MC9S12C-Family / MC9S12GC-Family Rev 01.24 6-2. Registers are accessed by Access — R/W — R/W R — Freescale Semiconductor ...

Page 169

... R X Reserved W 0xFF06 R CCR7 BDMCCR W 0xFF07 R 0 BDMINR W 0xFF08 R 0 Reserved W 0xFF09 R 0 Reserved W 0xFF0A R X Reserved W 0xFF0B R X Reserved W = Unimplemented, Reserved X = Indeterminate Freescale Semiconductor Chapter 6 Background Debug Module (BDMV4) Block Description BDMACT SDV ENTAG CCR6 CCR5 CCR4 REG14 REG13 REG12 ...

Page 170

... ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does not apply in special single-chip mode). 170 BDMACT SDV ENTAG Unimplemented or Reserved Figure 6-3. BDM Status Register (BDMSTS) MC9S12C-Family / MC9S12GC-Family Rev 01. TRACE UNSEC CLKSW ( Implemented (do not alter) Freescale Semiconductor ...

Page 171

... It will stay set as long as continuous back-to-back TRACE1 commands are executed. This bit will get cleared when the next command that is not a TRACE1 command is recognized. 0 TRACE1 command is not being executed 1 TRACE1 command is being executed Freescale Semiconductor Chapter 6 Background Debug Module (BDMV4) Block Description Table 6-2. BDMSTS Field Descriptions Description MC9S12C-Family / MC9S12GC-Family Rev 01 ...

Page 172

... PLLSEL CLKSW 0 0 Bus clock 0 1 Bus clock 1 0 Alternate clock (refer to the device overview chapter to determine the alternate clock source Bus clock dependent on the PLL 172 Description Table 6-3. BDM Clock Sources BDMCLK MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 173

... Internal Register Map Position — These four bits show the state of the upper five bits of the base address for REG[14:11] the system’s relocatable register block. BDMINR is a shadow of the INITRG register which maps the register block to any 2K byte space within the first 32K bytes of the 64K byte address space. Freescale Semiconductor Chapter 6 Background Debug Module (BDMV4) Block Description 5 4 ...

Page 174

... BDM is enabled and active immediately out of special single-chip reset. 2. This method is only available on systems that have a a breakpoint or a debug sub-block. 174 Commands.” Target system memory Commands.” The CPU resources referred to are the Commands.” Firmware commands can only be executed MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 175

... CPU operation provided that it can be completed in a single cycle. However operation requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle. Freescale Semiconductor Chapter 6 Background Debug Module (BDMV4) Block Description NOTE MC9S12C-Family / MC9S12GC-Family Rev 01 ...

Page 176

... Odd address data on low byte; even address data on high byte. 16-bit address Write to memory with standard BDM firmware lookup table out of map. 16-bit data in Must be aligned access. Section 6.4.2, “Enabling and Activating MC9S12C-Family / MC9S12GC-Family Rev 01.24 Description BDM.” Freescale Semiconductor ...

Page 177

... If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. Freescale Semiconductor Chapter 6 Background Debug Module (BDMV4) Block Description Table 6-6 ...

Page 178

... Target clock cycles are cycles measured using the target MCU’s serial clock rate. See and Section 6.3.2.1, “BDM Status Register 178 NOTE NOTE NOTE (BDMSTS),” for information on how serial clock rate is selected. MC9S12C-Family / MC9S12GC-Family Rev 01.24 1 Section 6.4.6, “BDM Serial Interface,” Freescale Semiconductor ...

Page 179

... The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle Freescale Semiconductor Chapter 6 Background Debug Module (BDMV4) Block Description ...

Page 180

... The host should sample the bit level about 10 target clock cycles after it started the bit time. 180 TARGET SENSES BIT 10 CYCLES Figure 6-8 shows the host receiving a logic 1 from the target MC9S12C-Family / MC9S12GC-Family Rev 01.24 EARLIEST START OF NEXT BIT Freescale Semiconductor ...

Page 181

... BKGD PIN TARGET SYS. DRIVE AND SPEEDUP PULSE PERCEIVED START OF BIT TIME BKGD PIN Figure 6-9. BDM Target-to-Host Serial Bit Timing (Logic 0) Freescale Semiconductor Chapter 6 Background Debug Module (BDMV4) Block Description HIGH-IMPEDANCE R-C RISE 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN HIGH-IMPEDANCE ...

Page 182

... BDM command was not executed. After entering wait or stop mode, the BDM command is no longer pending. 182 Figure 6-10). This pulse is referred to as the ACK pulse. 16 CYCLES SPEEDUP PULSE MINIMUM DELAY FROM THE BDM COMMAND NOTE MC9S12C-Family / MC9S12GC-Family Rev 01.24 HIGH-IMPEDANCE EARLIEST START OF NEXT BIT Freescale Semiconductor ...

Page 183

... ACK would be prevented from being issued. If not aborted, the ACK would remain pending indefinitely. See the handshake abort procedure described in Section 6.4.8, “Hardware Handshake Abort Freescale Semiconductor Chapter 6 Background Debug Module (BDMV4) Block Description BDM DECODES BDM EXECUTES THE ...

Page 184

... Note that, after the command is aborted a new command could be issued by the host computer. Figure 6-12 does not represent the signals in a true timing scale 184 Pulse,” and assumes that the pending command NOTE NOTE MC9S12C-Family / MC9S12GC-Family Rev 01.24 Section 6.4.9, “SYNC — Request Freescale Semiconductor ...

Page 185

... It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device. If desired, without the need for waiting for the ACK pulse. Freescale Semiconductor Chapter 6 Background Debug Module (BDMV4) Block Description SYNC RESPONSE ...

Page 186

... SYNC command. The TAGGO command will not issue an ACK pulse because this would interfere with the tagging function shared on the same pin. 186 Commands,” and Section 6.4.4, “Standard BDM Firmware MC9S12C-Family / MC9S12GC-Family Rev 01.24 Commands,” Freescale Semiconductor ...

Page 187

... BDM firmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time. Freescale Semiconductor Chapter 6 Background Debug Module (BDMV4) Block Description MC9S12C-Family / MC9S12GC-Family Rev 01 ...

Page 188

... MCU. This is referred soft-reset. 188 NOTE Table 6-7. Tag Pin Function TAGHI TAGLO Tag tag 1 0 Low byte 0 1 High byte 0 0 Both bytes MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 189

... As the clocks restart from stop mode, the BDM receives a soft reset (clearing any command in progress) and the ACK function will be disabled. This is a change from previous BDM modules. Freescale Semiconductor Chapter 6 Background Debug Module (BDMV4) Block Description MC9S12C-Family / MC9S12GC-Family Rev 01 ...

Page 190

... Chapter 6 Background Debug Module (BDMV4) Block Description 190 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 191

... Compare on address 256 byte (range) — Compare on any 16K page (page) • At forced breakpoints compare address on read or write • High and/or low byte data compares • Comparator C can provide an additional tag or force breakpoint (enhancement for BKP mode) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24 191 ...

Page 192

... Source address of taken conditional branches (long, short, bit-conditional, and loop constructs) — Destination address of indexed JMP, JSR, and CALL instruction. — Destination address of RTI, RTS, and RTC instructions — Vector address of interrupts, except for SWI and BDM vectors 192 MC9S12C-Family / MC9S12GC-Family Rev 01.24 Freescale Semiconductor ...

Page 193

... Detail: save all bus operations except program and free cycles — Profile: poll target from external device 7.1.3 Block Diagram Figure 7 block diagram of this module in breakpoint mode. module in debug mode. Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description Figure 7-2 MC9S12C-Family / MC9S12GC-Family Rev 01. block diagram of this 193 ...

Page 194

... COMPARATOR COMPARATOR COMPARATOR COMPARATOR MC9S12C-Family / MC9S12GC-Family Rev 01.24 BKP CONTROL SIGNALS . . . . . . EXPANSION ADDRESSES ADDRESS HIGH ADDRESS LOW EXPANSION ADDRESSES DATA HIGH DATA/ADDRESS ADDRESS HIGH HIGH MUX DATA LOW DATA/ADDRESS ADDRESS LOW LOW MUX READ DATA HIGH READ DATA LOW Freescale Semiconductor ...

Page 195

... MEBI) may also be a part of the breakpoint operation. Table 7-1. External System Pins Associated with DBG and MEBI Pin Name Pin Functions BKGD/MODC/ TAGHI TAGHI PE3/LSTRB/ TAGLO TAGLO Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description ADDRESS/DATA/CONTROL CONTROL REGISTERS MATCH_A COMPARATOR A MATCH_B COMPARATOR B ...

Page 196

... Table 7-2. DBGV1 Memory Map Use ARM TRGSEL BEGIN Unimplemented or Reserved Figure 7-3. DBG Register Summary MC9S12C-Family / MC9S12GC-Family Rev 01.24 Figure 7-3. Detailed Access R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R DBGBRK CAPMOD TRG Freescale Semiconductor Bit 0 ...

Page 197

... Bit 7 W BKP0L 0x002D R DBGCBX PAGSEL W BKP1X 0x002E R DBGCBH Bit 15 W BKP1H 0x002F R DBGCBL Bit 7 W BKP1L Figure 7-3. DBG Register Summary (continued) Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description Bit 14 Bit 13 Bit 12 Bit 6 Bit 5 Bit FULL BDM TAGAB BKAMBL ...

Page 198

... Table 7-3. DBGC1 Field Descriptions Description Module,” for more information. Selection,” for more information. TRGSEL may also determine the type of breakpoint B.” Begin-Trigger,” and Section 7.4.2.8.2, “Storing with MC9S12C-Family / MC9S12GC-Family Rev 01. CAPMOD Section 7.4.3.1, End-Trigger,” for Freescale Semiconductor ...

Page 199

... In profile mode, the debugger is returning the address of the last instruction executed by the CPU on each access of trace buffer address. Refer to Section 7.4.2.6, “Capture Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description Description Table 7-4 for capture mode fi ...

Page 200

... 0010 A then B 0011 Event only B 0100 A then event only B 0101 A and B (full mode) 0110 A and Not B (full mode) 0111 Inside range 1000 Outside range 1001 Reserved ↓ (Defaults to A only) 1111 MC9S12C-Family / MC9S12GC-Family Rev 01. TRG Table 7-6. See Freescale Semiconductor ...