MC9S12C32CFAE25 Freescale Semiconductor, MC9S12C32CFAE25 Datasheet - Page 89

• Manufacturer Part Number: MC9S12C32CFAE25
• Description: IC MCU 32K FLASH 25MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32CFAE25

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 31
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.3.2.3
2.3.2.3.1
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The SPI pin configurations (PM[5:2]) is determined by several status bits in the SPI module. Please refer
to the SPI Block User Guide for details.
2.3.2.3.2
Read: Anytime.
Write: Never, writes to this register have no effect.
Freescale Semiconductor
Module Base + 0x0010
Module Base + 0x0011
MSCAN/
PTIM[5:0]
Reset
Reset
Field
5–0
SPI
W
W
R
R
Port M Input Register — This register always reads back the status of the associated pins. This also can be
used to detect overload or short circuit conditions on output pins.
Port M Registers
—
—
0
0
0
7
7
Port M I/O Register (PTM)
Port M Input Register (PTIM)
= Unimplemented or Reserved
= Unimplemented or Reserved
—
—
0
0
0
6
6
Figure 2-18. Port M Input Register (PTIM)
Figure 2-17. Port M I/O Register (PTM)
Table 2-16. PTIM Field Descriptions
PTIM5
PTM5
MC9S12C-Family / MC9S12GC-Family
SCK
—
0
5
5
PTIM4
PTM4
MOSI
Rev 01.24
—
0
4
4
Description
Chapter 2 Port Integration Module (PIM9C32) Block Description
PTIM3
PTM3
SS
—
0
3
3
PTIM2
PTM2
MISO
—
0
2
2
TXCAN
PTIM1
PTM1
—
0
1
1
RXCAN
PTIM0
PTM0
—
0
0
0
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