MC9S12C32CFAE25 Freescale Semiconductor, MC9S12C32CFAE25 Datasheet - Page 468

• Manufacturer Part Number: MC9S12C32CFAE25
• Description: IC MCU 32K FLASH 25MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32CFAE25

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 31
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description
16.4.1
VREG3V3V2, respectively its regulator core has two parallel, independent regulation loops (REG1 and
REG2) that differ only in the amount of current that can be sourced to the connected loads. Therefore, only
REG1 providing the supply at V
The regulator is a linear series regulator with a bandgap reference in its Full Performance Mode and a
voltage clamp in Reduced Power Mode. All load currents flow from input V
reference circuits are connected to V
16.4.2
In Full Performance Mode, a fraction of the output voltage (V
fed to an operational amplifier. The amplified input voltage difference controls the gate of an output driver
which basically is a large NMOS transistor connected to the output.
16.4.3
In Reduced Power Mode, the driver gate is connected to a buffered fraction of the input voltage (V
The operational amplifier and the bandgap are disabled to reduce power consumption.
16.4.4
sub-block LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input
voltage (V
status flag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode
and Shutdown Mode.
16.4.5
This functional block monitors output V
V
Due to its role during chip power-up this module must be active in all operating modes of VREG3V3V2.
16.4.6
Block LVR monitors the primary output voltage V
LVR asserts and when rising above the deassertion level (V
function is available only in Full Performance Mode.
16.4.7
This part contains the register block of VREG3V3V2 and further digital functionality needed to control
the operating modes. CTRL also represents the interface to the digital core logic.
468
PORD
, the signal goes low. The transition to low forces the CPU in the power-on sequence.
DDA
REG — Regulator Core
Full-Performance Mode
Reduced-Power Mode
LVD — Low-Voltage Detect
POR — Power-On Reset
LVR — Low-Voltage Reset
CTRL — Regulator Control
–V
SSA
) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever
DD
/V
MC9S12C-Family / MC9S12GC-Family
DDA
SS
DD
is explained. The principle is also valid for REG2.
and V
. If V
SSA
Rev 01.24
DD
DD
.
is below V
. If it drops below the assertion level (V
LVRD
DD
PORD
) and the bandgap reference voltage are
) signal LVR negates again. The LVR
, signal POR is high, if it exceeds
DDR
to V
Freescale Semiconductor
SS
or V
LVRA
SSPLL
) signal
DDR
, the
).