M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet
M30800SAGP-BL#U5
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M30800SAGP-BL#U5 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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M32C/80 Group 16/ 32 Hardware Manual RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to ...
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Keep safety first in your circuit designs! Renesas Technology Corp. puts the maximum effort into making semiconductor products 1. better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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Introduction This hardware manual provides detailed information on the M32C/80 Group microcomputers. Users are ex- pected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in ...
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M16C Family Documents The following documents were prepared for the M16C family. Document Short Sheet Data Sheet Hardware Manual Software Manual Application Note RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc. NOTES : ...
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Table of Contents Quick Reference by Address _____________________ B-1 1. Overview _____________________________________ 1 1.1 Applications ................................................................................................................ 1 1.2 Performance Overview .............................................................................................. 2 1.3 Block Diagram ............................................................................................................ 3 1.4 Product Information ................................................................................................... 4 1.5 Pin Assignment .......................................................................................................... 5 1.6 Pin Description ...
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Bus_________________________________________ 39 7.1 Bus Settings ............................................................................................................. 39 7.1.1 Selecting External Address Bus ...................................................................... 40 7.1.2 Selecting External Data Bus ............................................................................ 40 7.1.3 Selecting Separate/Multiplexed Bus ............................................................... 40 7.2 Bus Control ............................................................................................................... 42 7.2.1 Address Bus and Data Bus .............................................................................. ...
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Software Interrupts ................................................................................................ 83 10.2.1 Undefined Instruction Interrupt ..................................................................... 83 10.2.2 Overflow Interrupt ........................................................................................... 83 10.2.3 BRK Interrupt .................................................................................................. 83 10.2.4 BRK2 Interrupt ................................................................................................ 83 10.2.5 INT Instruction Interrupt ................................................................................. 83 10.3 Hardware Interrupts ............................................................................................... 84 10.3.1 Special Interrupts ...
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DMAC II ___________________________________ 120 13.1 DMAC II Settings .................................................................................................. 120 13.1.1 RLVL Register................................................................................................ 120 13.1.2 DMAC II Index ................................................................................................ 122 13.1.3 Interrupt Control Register for the Peripheral Function ............................. 124 13.1.4 Relocatable Vector Table for the Peripheral Function ............................... ...
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Clock Asynchronous Serial I/O (UART) Mode ................................................... 183 16.2.1 Bit Rate .......................................................................................................... 187 16.2.2 Selecting LSB First or MSB First ................................................................. 188 16.2.3 Serial Data Logic Inverse ............................................................................. 188 16.2.4 TxD and RxD I/O Polarity Inverse ................................................................ 189 16.3 ...
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D/A Converter ______________________________ 236 19. CRC Calculation ____________________________ 239 20. X/Y Conversion _____________________________ 241 21. Intelligent I/O_______________________________ 244 21.1 Communication Unit 0 and 1 Communication Function .................................. 246 21.1.1 Clock Synchronous Serial I/O Mode (Communication Units 0 and 1) ...
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INT Interrupt .................................................................................................. 315 24.6.4 Watchdog Timer Interrupt ............................................................................ 316 24.6.5 Changing Interrupt Control Register .......................................................... 316 24.6.6 Changing IIOiIR Register ( ............................................................ 316 24.6.7 Changing RLVL Register .............................................................................. 316 24.7 DMAC .................................................................................................................... 317 ...
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Quick Reference by Address Quick Reference by Address Address Register 0000 16 0001 16 0002 16 0003 16 0004 Processor Mode Register 0 (PM0) 16 0005 Processor Mode Register 1 (PM1) 16 0006 System Clock Control Register 0 (CM0) 16 ...
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Quick Reference by Address Address Register 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 DMA0 Interrupt Control Register (DM0IC) 16 0069 Timer B5 Interrupt Control Register (TB5IC) 16 006A DMA2 Interrupt ...
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Quick Reference by Address Address Register 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD 16 00CE 16 00CF 16 00D0 16 ...
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Quick Reference by Address Address Register 0120 16 0121 16 0122 16 0123 16 0124 16 0125 16 0126 16 0127 16 0128 16 SI/O Receive Buffer Register 1 (G1RB) 0129 16 012A Transmit Buffer/Receive Data Register 1 (G1TB/G1DR) 16 ...
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Quick Reference by Address Address Register 02B0 16 02B1 16 02B2 16 02B3 16 02B4 16 02B5 16 02B6 16 02B7 16 02B8 16 02B9 16 02BA 16 02BB 16 02BC 16 02BD 16 02BE 16 02BF 16 02C0 16 ...
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Quick Reference by Address Address Register 0310 16 Timer B3 Register (TB3) 0311 16 0312 16 Timer B4 Register (TB4) 0313 16 0314 16 Timer B5 Register (TB5) 0315 16 0316 16 0317 16 0318 16 0319 16 031A 16 ...
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Quick Reference by Address Address Register 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 DMA0 Request Source Select Register (DM0SL) 16 0379 DMA1 Request Source Select Register (DM1SL) 16 037A DMA2 ...
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Quick Reference by Address Address Register 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA Pull-Up Control Register 2 (PUR2) 16 03DB Pull-Up Control Register 3 (PUR3) 16 ...
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M32C/80 Group SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER 1. Overview The M32C/80 Group microcomputer is a single-chip control unit that utilizes high-performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/80 Group is available in 100-pin plastic molded LQFP/QFP ...
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1.2 Performance Overview Table 1.1 lists performance overview of the M32C/80 Group. Table 1.1 M32C/80 Group Performance Item CPU Basic Instructions Minimum Instruction Execution Time Operating Mode Memory ...
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1.3 Block Diagram Figure 1.1 shows a block diagram of the M32C/80 Group microcomputer. 8 (1) Port P0 Peripheral Functions Timer (16 bits) Timer A: 5 channels Timer ...
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1.4 Product Information Table 1.2 lists the product information. Figure 1.2 shows the product numbering system. Table 1.2 M32C/80 Group ...
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1.5 Pin Assignment Figures 1.3 and 1.4 show pin assignments (top view ...
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...
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Table 1.3 Pin Characteristics Package Control Interrupt Pin No Port pins pins 100 ...
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Table 1.3 Pin Characteristics (Continued) Package Control Interrupt pin No Port pins pins ...
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1.6 Pin Description Table 1.4 Pin Description Signal name Pin name I/O type Power supply V V CC1, CC2 V SS Analog power AV CC supply input AV ...
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Table 1.4 Pin Description (Continued) Signal name Pin name I/O type Main clock input X IN Main clock X OUT output Sub clock input X CIN Sub clock ...
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Table 1.5 Pin Description (Continued) Signal name Pin name I/O type Reference V REF voltage input A/D converter ___________ AD TRG ANEX0 ANEX1 ...
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Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The register bank is comprised of 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) ...
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2.1 General Registers 2.1.1 Data Registers (R0, R1, R2 and R3) R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 ...
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2.1.8.5 Register Bank Select Flag (B) The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this ...
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Memory Figure 3.1 shows a memory map of the M32C/80 Group. The M32C/80 Group provides 16-Mbyte address space addressed from 000000 The fixed interrupt vectors are allocated ...
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Special Function Registers (SFRs) Address 0000 16 0001 16 0002 16 0003 16 0004 Processor Mode Register 16 0005 Processor Mode Register 1 16 0006 System Clock ...
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Address Register 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 Address Match Interrupt Register 6 16 003A ...
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Address 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 DMA0 Interrupt Control Register 16 0069 Timer B5 Interrupt Control ...
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Address 0090 UART0 Transmit /NACK Interrupt Control Register 16 0091 UART1/UART4 Bus Conflict Detect Interrupt Control Register 16 0092 UART1 Transmit/NACK Interrupt Control Register 16 0093 Key Input ...
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Address 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD ...
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Address 00F0 Data Compare Register 00 16 00F1 Data Compare Register 01 16 00F2 Data Compare Register 02 16 00F3 Data Compare Register 03 16 00F4 Data Mask ...
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Address 0120 16 0121 16 0122 16 0123 16 0124 16 0125 16 0126 16 0127 16 0128 16 SI/O Receive Buffer Register 1 0129 16 012A Transmit ...
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Address 02B1 16 02B2 16 02B3 16 02B4 16 02B5 16 02B6 16 02B7 16 02B8 16 02B9 16 02BA 16 02BB 16 02BC 16 02BD 16 02BE ...
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Address 02E0 X/Y Control Register 16 02E1 16 02E2 16 02E3 16 02E4 UART1 Special Mode Register 4 16 02E5 UART1 Special Mode Register 3 16 02E6 UART1 ...
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Address 0310 16 Timer B3 Register 0311 16 0312 16 Timer B4 Register 0313 16 0314 16 Timer B5 Register 0315 16 0316 16 0317 16 0318 16 ...
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Address 0340 Count Start Flag 16 0341 Clock Prescaler Reset Flag 16 0342 One-Shot Start Flag 16 0343 Trigger Select Register 16 0344 Up/Down Flag 16 0345 16 ...
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Address 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 DMA0 Request Source Select Register 16 0379 DMA1 Request Source ...
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Address 03A0 16 03A1 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 Function Select Register D1 16 03A8 16 03A9 16 03AA 16 03AB ...
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Address 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA Pull-Up Control Register 2 16 03DB ...
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Reset Hardware reset 1, software reset, and watchdog timer reset are available to reset the microcomputer. 5.1 Hardware Reset 1 Pins, the CPU and SFRs are reset ...
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CC1 CC2 td(P- more is equired RESET BCLK Microprocessor Mode BYTE="H" Address A23 RD WR Microprocessor Mode BYTE="L" Address ...
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Table 5.1 Pin States while RESET Pin is Held "L" Pin Name CNV SS P0 Input port (high-impedance) Inputs data (high-impedance) P1 Input port (high-impedance) Inputs data (high-impedance) ...
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5.2 Software Reset Pins, the CPU and SFRs are reset when the PM03 bit in the PM0 register is set to "1" (microcomputer reset). Then the microcomputer executes ...
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Processor Mode NOTE The M32C/80 Group is ROMless device. Connect the CNV Use the M32C/80 Group in microprocessor mode after reset. 6.1 Types of Processor Mode Single-chip ...
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6.2 Setting of Processor Mode The CNV pin state and the PM01 and PM00 bit settings in the PM0 register determine which processor SS mode is selected. Table ...
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Processor Mode Register NOTES: 1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set ...
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Processor Mode Register NOTES: 1. Rewrite the PM1 register after the PRC1 bit in the PRCR register is ...
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Figure 6.3 Memory Map in Each Processor Mode Page ...
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Bus In memory expansion mode or microprocessor mode, some pins function as bus control pins to control the address bus and data bus. A _________ _________ _______ ...
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7.1.1 Selecting External Address Bus The number of externally-output address buses, the number of chip-select signals and chip-select-as- _____ signed address space (CS area) vary depending on each ...
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Table 7.2 Processor Mode and Port Function Single- Processor Chip Mode Mode PM05 to Access CS1 or CS2 using PM04 Bits in PM0 Register Access All Other CS ...
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7.2 Bus Control Signals, required to access external devices, are provided and software wait states are inserted as follows. The signals are available in memory expansion mode and ...
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Example 1: When the microcomputer accesses the external space j specified by another chip-select signal in the next cycle after having accessed the external space i, both address ...
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7.2.3 Read and Write Signals When using a 16-bit data bus, the PM02 bit in the PM0 register selects a combination of the "RD, WR and ________ _____ ...
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7.2.4 Bus Timing Bus cycle for the internal memory is basically one BCLK cycle. When the PM12 bit in the PM1 register is set to "1" (wait state), ...
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Table 7.5 Software Wait State and Bus Cycle ...
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• Bus Cycle bus cycle = 2 BCLK Address ( Data (Read) RD Data (Write) WR, WRL, WRH • Bus Cycle 1 ...
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• Bus Cycle bus cycle = 4 BCLK Address ( Data (Read) RD Data (Write) WR, WRL, WRH • Bus Cycle 2 ...
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• Bus Cycle Data (Read) Data (Write) WR, WRL, WRH • Bus Cycle Data (Read) Data (Write) WR, WRL, WRH • Bus ...
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• Bus Cycle bus cycle = 4 BCLK ( Data (Read Data (Write (WRL) ALE • Bus Cycle ...
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• Bus Cycle Data (Read) Data (Write) WR (WRL) • Bus Cycle Data (Read) Data (Write) WR (WRL) • Bus Cycle 3 ...
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7.2.4.1 Bus Cycle with Recovery Cycle Added The EWCRi06 bit in the EWCRi register (i determines whether the recovery cycle is added or not. In the ...
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7.2.5 ALE Signal The ALE signal latches an address of the multiplexed bus. Latch an address on the falling edge of the ALE signal. The PM15 and PM14 ...
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(1) Separate Bus with 2 Wait States 1st cycle BCLK RDY (2) Multiplexed Bus with 2 Wait States 1st cycle BCLK ...
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_________ 7.2.7 HOLD Signal __________ The HOLD signal transfers bus privileges from the CPU to external circuits. When a low-level ("L") signal is __________ applied to the HOLD ...
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Clock Generation Circuit 8.1 Types of the Clock Generation Circuit Four circuits are included to generate the system clock signal: • Main clock oscillation circuit • Sub ...
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Figure 8.1 Clock Generation Circuit Page ...
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System Clock Control Register NOTES: 1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set ...
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System Clock Control Register NOTES: 1. Rewrite the CM1 register after the PRC0 bit ...
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Main Clock Division Register NOTES: 1. Rewrite the MCD register after the PRC0 bit in the PRCR register is set to ...
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Oscillation Stop Detection Register NOTES: 1. Rewrite the CM2 register after the PRC0 bit in the PRCR ...
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Count Source Prescaler Register NOTES: 1. Rewrite the CNT3 to CNT0 bits after the CST bit is set to "0". 2. ...
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PLL Control Register NOTES: 1. Rewrite the PLC0 register after the PRC0 bit in the PRCR register is ...
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Processor Mode Register NOTES: 1. Rewrite the PM2 register after the PRC1 bit in the ...
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8.1.1 Main Clock Main clock oscillation circuit generates the main clock. The main clock becomes clock source of the CPU clock and peripheral function clock. The main clock ...
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8.1.2 Sub Clock Sub clock oscillation circuit generates the sub clock. The sub clock becomes clock source of the CPU clock and for the timers A and B. ...
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8.1.3 On-Chip Oscillator Clock On-chip oscillator generates the on-chip oscillator clock. The 1-MHz on-chip oscillator clock becomes a clock source of the CPU clock and peripheral function clock. ...
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"01000 (main clock as CPU clock source) Figure 8.11 Switching Procedure from On-chip Oscillator Clock to Main Clock ...
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8.1.4 PLL Clock The PLL frequency synthesizer generates the PLL clock based on the main clock. The PLL clock can be used as clock source for the CPU ...
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8.2 CPU Clock and BCLK The CPU operating clock is referred to as the CPU clock. The CPU clock is also a count source for the watchdog timer. ...
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8.3.3 f C32 f is the sub clock divided by 32. f C32 when the sub clock is running. 8.4 Clock Output Function The CLK pin outputs f ...
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8.5 Power Consumption Control Normal operating mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, ...
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Switch the CPU clock after the clock to be switched to stabilize. Sub clock oscillation will take longer stabilize. Wait, by program, until the clock stabilizes directly after ...
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8.5.2.3 Pin Status in Wait Mode Table 8.7 lists pin states in wait mode. Table 8.7 Pin States in Wait Mode Pin _______ Address Bus, Data Bus, CS0 ...
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Table 8.8 Interrupts to Exit Wait Mode ...
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8.5.3.1 Entering Stop Mode Stop mode is entered when setting the CM10 bit in the CM1 register to "1" (all clocks stops). The MCD4 to MCD0 bits in ...
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8.5.3.3 Pin Status in Stop Mode Table 8.9 lists pin status in stop mode. Table 8.9 Pin Status in Stop Mode Pin _______ Address Bus, Data Bus, CS0 ...
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All oscillation is stopped CM10=1 Stop Mode Interrupt Stop Mode CM10=1 (Note 2) NOTES: 1. See Figure 8.14. 2. When the CM17 bit is set to "1" (PLL ...
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Figure 8.14 Status Transition Page ...
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8.6 System Clock Protect Function The system clock protect function prohibits the CPU clock from changing clock sources when the main clock is selected as the CPU clock ...
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Protection The protection function protects important registers from being easily overwritten when a program runs out of control. Figure 9.1 shows the PRCR register. Each bit in ...
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10. Interrupts 10.1 Types of Interrupts Figure 10.1 shows types of interrupts. Software (Non-Maskable Interrupt) Interrupt Hardware NOTES: 1. The peripheral functions in the microcomputer are used to ...
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10.2 Software Interrupts Software interrupt occurs when an instruction is executed. The software interrupts are non-maskable inter- rupts. 10.2.1 Undefined Instruction Interrupt The undefined instruction interrupt occurs when ...
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10.3 Hardware Interrupts Special interrupts and peripheral function interrupts are available as hardware interrupts. 10.3.1 Special Interrupts Special interrupts are non-maskable interrupts. ______ 10.3.1.1 NMI Interrupt ______ The ...
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10.4 High-Speed Interrupt The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt in three cycles. When the FSIT bit in the RLVL ...
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10.5.1 Fixed Vector Tables The fixed vector tables are allocated addresses FFFFDC tables. Table 10.1 Fixed Vector Table ...
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Table 10.2 Relocatable Vector Tables Interrupt Generated by (2) BRK Instruction Reserved Space DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 (3) ...
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Table 10.2 Relocatable Vector Tables (Continued) Interrupt Generated by Bus Conflict Detect, Start Condition Detect, +156 to +159 (009C Stop Condition Detect (UART2) Bus Conflict Detect, Start Condition ...
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10.6 Interrupt Request Acknowledgement Software interrupts and special interrupts occur when conditions to generate an interrupt are met. The peripheral function interrupts are acknowledged when all conditions below ...
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Interrupt Control Register NOTES: 1. The BCN0IC register shares an address with the BCN3IC register. 2. The BCN1IC register shares an ...
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Interrupt Control Register NOTES: 1. When a 16-bit data bus is used in microprocessor or memory expansion mode, each INT3 to ...
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Exit Priority Register NOTES: 1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than ...
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10.6.3 Interrupt Sequence The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine execution. When an interrupt request is generated while an instruction is executed, ...
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10.6.4 Interrupt Response Time Figure 10.6 shows an interrupt response time. Interrupt response time is the period between an interrupt generation and the execution of the first instruction ...
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Table 10.4 Interrupt Sequence Execution Time Interrupt Peripheral Function INT Instruction _______ NMI Watchdog Timer Undefined Instruction Address Match Overflow BRK Instruction (relocatable vector table) BRK Instruction (fixed ...
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10.6.6 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After the FLG register is saved to the stack, 16 ...
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10.6.8 Interrupt Priority If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an interrupt request is generated or not), ...
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High Each Interrupt Priority Level DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 Transmission/NACK UART0 Reception/ACK UART1 Transmission/NACK UART1 Reception/ACK Timer ...
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______ 10.7 INT Interrupt External input generates the INTi interrupt ( 5). The LVS bit in the INTiIC register selects either edge sensitive triggering to ...
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______ 10.8 NMI Interrupt ______ (1) The NMI interrupt occurs when a signal applied to the NMI pin changes from a high-level ("H") signal to a ______ low-level ...
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10.10 Address Match Interrupt The address match interrupt occurs immediately before executing an instruction that is stored into an ad- dress indicated by the RMADi register (i=0 to ...
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10.11 Intelligent I/O Interrupt The intelligent I/O interrupt is assigned to software interrupt numbers 44 to 48. When using the intelligent I/O interrupt, set the IRLT bit in ...
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Interrupt Request Register NOTES: 1. See table below for bit symbols. 2. Only "0" can be set (nothing ...
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Interrupt Enable Register NOTES: 1. See table below for bit symbols interrupt request is used ...
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11. Watchdog Timer The watchdog timer monitors the program executions and detects defective program. It allows the micro- computer to trigger a reset or to generate an interrupt ...
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Watchdog Timer Control Register Watchdog Timer Start Register b7 NOTE: 1. Write the WDTS register after the watchdog timer interrupt ...
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System Clock Control Register NOTES: 1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set ...
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11.1 Count Source Protection Mode In count source protection mode, the on-chip oscillator clock is used as a count source for the watchdog timer. The count source protection ...
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12. DMAC This microcomputer contains four DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC transmits a 8- ...
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DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i using an interrupt request, generated by the functions determined ...
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DMAi Request Source Select Register NOTES: 1. Change the DSEL4 to DSEL0 bit settings while the MDi1 and MDi0 bits in ...
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Table 12.2 DMiSL Register (i Function Setting Value DMA0 Falling Edge ...
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DMA Mode Register NOTE: 1. Use the LDC instruction to set the DMD0 register. DMA Mode Register ...
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DMAi Transfer Count Register b15 b8 b7 NOTES: 1. When the DCTi register is set to "0000 2. Use the LDC instruction to set the DCT0 and DCT1 ...
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DMAi Memory Address Register b23 b16 b15 NOTES: 1. When the RWk bit (k the DMDj register (j=0, 1)is set to "0" (fixed address to ...
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12.1 Transfer Cycle Transfer cycle contains a bus cycle to read data from a memory or the SFR area (source read) and a bus cycle to write data ...
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(1) When 8-bit data is transferred or when 16-bit data is transferred with a 16-bit data bus from an even source address CPU Clock Address CPU Use Bus ...
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12.2 DMAC Transfer Cycle The number of DMAC transfer cycle can be calculated as follows. Any combination of even or odd transfer read and write addresses are possible. ...
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When DMA transfer request signals by external source are applied to INT0 and INT1 simultaneously and a DMA transfer with minimum cycle occurs CPU Clock DMA0 DMA1 CPU ...
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13. DMAC II DMAC II performs memory-to-memory transfer, immediate data transfer and calculation transfer, which transfers the sum of two data added by an interrupt request from any ...
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Exit Priority Register NOTES: 1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than ...
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13.1.2 DMAC II Index The DMAC II index is a data table which comprises bytes (maximum 32 bytes when the multiple transfer function is selected). ...
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Table 13.2 DMAC II Index Configuration in Transfer Mode Memory-to-Memory Transfer Transfer Data /Immediate Data Transfer Chained Transfer Not Used Used End-of-Transfer Not Used Not Used Interrupt MOD ...
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13.1.3 Interrupt Control Register for the Peripheral Function For the peripheral function interrupt activating DMAC II, set the ILVL2 to ILVL0 bits to "111 13.1.4 Relocatable Vector Table ...
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13.3.2 Immediate Data Transfer DMAC II transfers immediate data to any memory location. A fixed or relocatable address can be se- lected as the destination address. Store the ...
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13.6 Chained Transfer The CHAIN bit in MOD selects the chained transfer. The following process initiates the chained transfer. (1) Transfer, caused by a transfer request source, occurs ...
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13.8 Execution Time DMAC II execution cycle is calculated by the following equations: Multiple transfers 21+ ( cycles Other than ...
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14. Timer The microcomputer has eleven 16-bit timers. Five timers A and six timers B have different functions. Each timer functions independently. The count source for each timer ...
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C32 TCK1 to TCK0 TB0 IN TCK1 and TCK0 TB1 IN TCK1 and ...
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14.1 Timer A Figure 14.3 shows a block diagram of the timer A. Figures 14.4 to 14.7 show registers associated with the timer A. The timer A supports ...
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Timer Ai Register b15 C32 NOTES: 1. Use 16-bit data for reading and writing. ...
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Timer Ai Mode Register Count Start Flag Figure 14.5 TA0MR to TA4MR Registers ...
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(1) Up/Down Flag NOTES: 1. Use the MOV instruction to set the UDF register. 2. This bit is enabled when the ...
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Trigger Select Register NOTE: 1. Overflow or underflow Count Source Prescaler Register NOTES: 1. ...
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Table 14.1 Pin Settings for Output from TAi Pin PS1, PS2 Registers OUT (1) P7 /TA0 PS1_0 /TA1 PS1_2 OUT P7 /TA2 PS1_4= ...
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14.1.1 Timer Mode In timer mode, the timer counts an internally generated count source (see Table 14.3). Figure 14.8 shows the TAiMR register (i timer ...
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Timer Ai Mode Register NOTES can be set to either "0" or "1". 2. The CNT3 ...
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14.1.2 Event Counter Mode In event counter mode, the timer counts how many external signals are applied or how many times another timer counter overflows and underflows. The ...
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Table 14.5 Event Counter Mode Specifications (When Processing Two-phase Pulse Signal on Timer A2, A3 and A4) Item Count Source Two-phase pulse signal applied to the TAi Counting ...
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Timer Ai Mode Register NOTES: 1. The TAiTGH and TAiTGL bits in the ONSF or TRGSR register determine ...
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14.1.2.1 Counter Reset by Two-Phase Pulse Signal Processing Z-phase input resets the timer counter when processing a two-phase pulse signal. This function can be used in timer A3 ...
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14.1.3 One-Shot Timer Mode In one-shot timer mode, the timer operates only once for each trigger (see Table 14.6). Once a trigger occurs, the timer starts and continues ...
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Timer Ai Mode Register NOTES: 1. The MR1 bit setting is enabled only when the TAiTGH and TAiTGL ...
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14.1.4 Pulse Width Modulation Mode In pulse width modulation mode, the timer outputs pulse of desired width continuously (see Table 14.7). The timer counter functions as either 16-bit ...
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Timer Ai Mode Register NOTES: 1. MR1 bit setting is enabled only when the TAiTGH and TAiTGL bits in ...
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When the reload register is set to "0003 of a signal applied to the TAi Count source Signal applied to TA pin iIN PWM pulse output from TA ...
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14.2 Timer B Figure 14.16 shows a block diagram of the timer B. Figures 14.17 to 14.19 show registers associated with the timer B. The timer B supports ...
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Timer Bi Mode Register NOTES: 1. Only MR2 bits in the TB0MR and TB3MR registers are enabled. 2. Nothing is assigned ...
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Timer B3, B4,B5 Count Start Flag Figure 14.19 TBSR Register Table 14.8 Settings for the TBi Port Name Function P9 TB0 ...
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14.2.1 Timer Mode In timer mode, the timer counts an internally generated count source (see Table 14.9). Figure 14.20 shows the TBiMR register (i timer ...
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14.2.2 Event Counter Mode In event counter mode, the timer counts how many external signals are applied or how many times another timer overflows and underflows. (See Table ...
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Timer Bi Mode Register NOTES: 1. MR0 and MR1 bit settings are enabled when the TCK1 bit is ...
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14.2.3 Pulse Period/Pulse Width Measurement Mode In pulse period/pulse width measurement mode, the timer measures pulse period or pulse width of an external signal. (See Table 14.11) Figure ...
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Timer Bi Mode Register (Pulse Period / Pulse Width Measurement Mode NOTES: 1. The MR1 and MR0 bits selects the ...
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Count source "H" Pulse to be measured "L" Timing to transfer value from counter to reload register Timing that the counter reaches "0000 " 16 TBiS bits in ...
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15. Three-Phase Motor Control Timer Functions Three-phase motor driving waveform can be output by using the timers A1, A2, A4 and B2. Table 15.1 lists specifications of the ...
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Table 15.2 Pin Settings Pin PS1, PS2 Registers P7 /V PS1_2 =1 2 PS1_3 = PS1_4 = PS1_5 = ...
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Figure 15.1 Three-Phase Motor Control Timer Functions Block Diagram Page 158 ...
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Three-Phase PWM Control Register NOTES: 1. Set the INVC0 register after the PRC1 bit in the PRCR register is ...
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Three-Phase PWM Control Register NOTES: 1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is ...
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Three-Phase Output Buffer Register NOTE: 1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift ...
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Timer B2 Interrupt Generation Frequency Set Counter b7 NOTES: 1. Use the MOV instruction to set the ICTB2 register the INV01 bit in the INVC0 register ...
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Timer B2 Register b15 NOTE: 1. Use a 16-bit data for read and write. Trigger Select Register NOTE: ...
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Timer Ai Mode Register NOTE: 1. The CNT3 to CNT0 bits in the TCSPR register select ...
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The three-phase motor control timer function is available by setting the INV02 bit in the INVC0 register to "1". The timer B2 is used for carrier wave control ...
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Sawtooth Waveform as a Carrier Wave Sawtooth Wave Signal Wave Timer B2 Timer A4 Start (1) Trigger Signal Timer A4 (1) One-Shot Pulse U-Phase (1) Output Signal U-Phase ...
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16. Serial I/O Serial I/O consists of five channels (UART0 to UART4). Each UARTi (i has an exclusive timer to generate the transfer clock and operates ...
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RxD Polarity RxDi Switching Circuit Selecting Clock Source 00 CKDIR f 1 Internal (2) 2n CLK1 and 1 CLK0 External Clock Synchronous ...
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UARTi Transmit Buffer Register b15 b8 b7 NOTE: 1. Use the MOV instruction to set the UiTB register. UARTi Receive Buffer Register b15 b8 b7 NOTES: 1. The ...
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UARTi Bit Rate Register b7 NOTES: 1. Use the MOV instruction to set the UiBRG register. 2. Set the UiBRG register while no data transfer occurs. 3. Set ...
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UARTi Transmit/Receive Control Register NOTES /TxD2 and The CNT3 to CNT0 bits in the TCSPR ...
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UARTi Transmit/Receive Control Register NOTES: 1. Set the SCLKSTPB/UiERE bit after setting the SMD2 to SMD0 bits in the UiMR register. ...
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UARTi Special Mode Register NOTES: 1. Refer to Table 16.14. 2. The external clock synchronous function can be selected by ...
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UARTi Special Mode Register NOTES: 1. Set the SS pin after the CRD bit in the UiC0 register is set ...
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UARTi Special Mode Register NOTE: 1. When each condition is generated, the STAREQ, RSTAREQ or STPREQ bit is set to ...
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External Interrupt Request Source Select Register NOTE: 1. Set this bit to "0" to select a level-sensitive triggering. When setting this ...
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16.1 Clock Synchronous Serial I/O Mode In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. Table 16.1 lists specifications of clock synchronous ...
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Table 16.2 Register Settings in Clock Synchronous Serial I/O Mode Register Bit UiTB UiRB OER UiBRG UiMR SMD2 to ...
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Table 16.3 Pin Settings in Clock Synchronous Serial I/O Mode (1) Port Function __________ P6 CTS0 input 0 __________ RTS0 output P6 CLK0 input 1 CLK0 output P6 ...