M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 175
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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R
R
M
e
E
3
. v
J
2
Figure 14.22 TB0MR to TB5MR Registers
0
C
1
9
0 .
8 /
B
0
0
0
2
7
G
N
Timer Bi Mode Register
(Pulse Period / Pulse Width Measurement Mode)
1
o
o r
b7
0 -
NOTES:
. v
u
1
b6
0
p
0
1. The MR1 and MR0 bits selects the following measurements.
2. The MR3 bit is indeterminate when reset.
3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
, 1
0
b5
To set the MR3 bit to "0", se the TBiMR register after the MR3 bit is set to "1" and one or more cycles
of the count source are counted, while the TBiS bits in the TABSR and TBSR registers are set to "1"
(starts counting).
The MR3 bit cannot be set to "1" by program.
2
Pulse period measurement 1 (the MR1 and MR0 bits are set to "00
Pulse period measurement 2 (the MR1 and MR0 bits are set to "01
Pulse width measurement (the MR1 and MR0 bits are set to "10
0
b4
0
Measures between the falling edge and the next falling edge of a pulse to be measured
Measures between the rising edge and the next rising edge of a pulse to be measured
Measures between a falling edge and the next rising edge of a pulse to be measured and
between the rising edge and the next falling edge of a pulse to be measured
5
b3
Page 154
b2
b1
1
b0
0
f o
TMOD0
TMOD1
Symbol
TCK0
TCK1
3
MR0
MR2
MR3
MR1
Bit
3
Symbol
TB0MR to TB5MR 035B
0
(i=0 to 5)
Operating Mode
Select Bit
Measurement Mode
Select Bit
TB0MR, TB3MR registers:
TB1MR, TB2MR TB4MR, TB5MR registers:
Timer Bi Overflow Flag
Count Source
Select Bit
Set to "0" in pulse period/pulse width measurement mode
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit Name
(1)
Address
16
, 035C
(2)
16
, 035D
b1b0
1 0: Pulse period measurement mode,
b3b2
0 0: Pulse period measurement 1
0 1: Pulse period measurement 2
1 0: Pulse width measurement
1 1: Do not set to this value
0: No overflow
1: Overflow
0 0: f
0 1: f
1 0: f
1 1: f
b7b6
Pulse width measurement mode
1
8
2n (3)
C32
16
, 031B
2
"):
2
2
"):
"):
16
Function
, 031C
16
, 031D
16
After reset
00XX 0000
14. Timer (Timer B)
RW
RW
RW
RW
RW
RW
RW
RW
RO
2
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