M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 209
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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e
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3
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J
2
Figure 16.17 Serial Data Logic Inverse
Figure 16.16 Transfer Format
0
C
16.2.2 Selecting LSB First or MSB First
1
16.2.3 Serial Data Logic Inverse
9
0 .
8 /
B
As shown in Figure 16.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format.
This function is available for 8-bit transfer data.
When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB
register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB
register. Figure 16.17 shows a switching example of the serial data logic.
0
0
0
2
7
G
N
1
o
o r
0 -
. v
u
1
Transfer Clock
Transfer Clock
0
p
(2) When the UiLCH bit in the UiC1 register is set to "1" (inverse)
0
(1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (no inverse)
(1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first)
(2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first)
, 1
0
NOTE:
(no inverse)
2
1. The above applies when the UFORM bit in the UiC0 register is set to "0" (
0
NOTE:
(inverse)
CLKi
CLKi
RxD
RxD
0
TxD
TxD
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
LSB first), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the
PRYE bit is set to "1" (parity enabled).
5
TxD
transmitted on the falling edge of the transfer clock and received on the rising edge)
and the UiLCH bit in the UiC1 register is set to "0" (no inverse).
TxD
i
i
i
i
Page 188
"H"
"H"
"H"
"H"
"H"
"H"
"L"
"L"
"L"
"L"
"L"
"L"
i
i
"H"
"H"
"H"
"H"
"L"
"L"
"L"
"L"
f o
ST
ST
ST
ST
3
ST
ST
3
0
D
D
D
D
0
0
7
7
D
D
0
0
D
D
D
D
1
1
6
6
D
D
1
1
D
D
D
D
2
2
5
5
D
D
2
2
D
D
D
D
3
3
4
4
D
D
D
D
3
3
D
D
4
4
3
3
D
D
D
D
D
D
4
4
5
5
2
2
D
D
D
D
D
D
5
5
6
6
1
1
D
D
D
D
D
D
7
7
6
6
0
0
D
P
P
D
P
P
7
7
SP
SP
SP
SP
P
P
ST: Start bit
P: Parity bit
SP: Stop bit
ST: Start bit
P: Parity bit
SP: Stop bit
SP
SP
16. Serial I/O (UART)
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