M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 132
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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M
R
R
e
E
3
. v
J
2
Figure 12.2 DM0SL to DM3SL Registers
0
C
1
9
8 /
0 .
B
0
0
0
2
G
7
N
1
o r
o
0 -
DMAi Request Source Select Register
. v
b7
u
NOTES:
1
p
0
0
b6
, 1
1. Change the DSEL4 to DSEL0 bit settings while the MDi1 and MDi0 bits in the DMD0 and DMD1
2. When the DSR bit is set to "1", set the DRQ bit to "1" simultaneously.
3. Do not set the DRQ bit to "0".
0
registers are set to "00
DSEL4 to DSEL0 bit settings are changed.
2
b5
0
0
e.g., MOV.B #083h, DMiSL ; Set timer A0
e.g., OR.B #0A0h, DMiSL
b4
5
b3
Page 111
b2
b1
b0
f o
2
Symbol
DSEL0
DSEL1
DSEL2
DSEL3
DSEL4
3
" (DMA disabled). Also, set the DRQ bit to "1" simultaneously when the
DRQ
DSR
(b6)
3
Bit
0
Symbol
DM0SL to DM3SL 0378
DMA Request Source
Select Bit
Software DMA
Request Bit
Reserved Bit
DMA Request Bit
Bit Name
(1)
(2)
Address
16,
(2, 3)
0379
(i=0 to 3)
16,
037A
See Table 12.2 for the DMiSL
register (i=0 to 3) function
When a software trigger is selected,
a DMA request is generated by
setting this bit to "1" (When read, its
content is always "0")
When read,
its content is indeterminate
0: Not requested
1: Requested
16,
037B
16
Function
After Reset
0X00 0000
2
RW
RW
RW
RW
RW
RW
RW
RW
RO
12. DMAC
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