M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 289
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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M
R
R
e
E
3
. v
J
2
Figure 22.6 P0 to P10 Registers
0
C
1
9
0 .
8 /
B
0
0
0
2
7
G
N
1
o
o r
0 -
. v
Port Pi Register
b7
u
1
NOTES:
p
0
0
, 1
b6
0
1. In memory expansion mode and microprocessor mode, the Pi register cannot control pins being used
2. P7
3. The P8_5 bit is for read only.
2
as bus control pins (A
BCLK/ALE/CLK
when P7
b5
0
0
0
5
b4
and P7
Page 268
b3
0
and P7
b2
1
are ports for the N-channel open drain output. The pins go into high-impedance states
b1
OUT
1
b0
(i=0 to 10)
output "H" signal.
, HLDA/ALE, HOLD, ALE and RDY).
f o
0
3
to A
Symbol
3
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Pi_5
Pi_6
Pi_7
Symbol
P0 to P5
P6 to P10
Bit
0
22
, A
(1)
23
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
, D
0
Address
03E0
03C0
to D
0
1
2
3
4
5
6
7
Bit Name
16
16
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
, 03E1
, 03C1
, CS0 to CS3, WRL/WR, WRH/BHE, RD,
16
16
, 03E4
(2)
, 03C4
16
, 03E5
16
Pin levels can be read by reading
bits corresponding to programmable
ports in input mode.
Pin levels can be controlled by
writing to bits corresponding to
programmable ports in output mode.
0: "L" level
1: "H" level
(3)
, 03C5
16
, 03E8
16
, 03C8
16
, 03E9
Function
16
16
22. Programmable I/O Ports
After Reset
Indeterminate
Indeterminate
RW
RW
RW
RW
RW
RW
RW
RW
RW
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