M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 35

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
2.2 High-Speed Interrupt Registers
2.3 DMAC-Associated Registers
e
E
3
. v
J
2
0
C
Registers associated with the high-speed interrupt are as follows:
Refer to 10.4 High-Speed Interrupt for details.
Registers associated with DMAC are as follows:
Refer to 12. DMAC for details.
1
9
0 .
8 /
B
- Flag save register (SVF)
- PC save register (SVP)
- Vector register (VCT)
- DMA mode register (DMD0, DMD1)
- DMA transfer count register (DCT0, DCT1)
- DMA transfer count reload register (DRC0, DRC1)
- DMA memory address register (DMA0, DMA1)
- DMA SFR address register (DSA0, DSA1)
- DMA memory address reload register (DRA0, DRA1)
0
0
2.1.8.5 Register Bank Select Flag (B)
2.1.8.6 Overflow Flag (O)
2.1.8.7 Interrupt Enable Flag (I)
2.1.8.8 Stack Pointer Select Flag (U)
2.1.8.9 Processor Interrupt Priority Level (IPL)
2.1.8.10 Reserved Space
0
2
The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this
flag is set to "1".
The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0".
The I flag enables a maskable interrupt.
Interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is
set to "0" when an interrupt is acknowledged.
ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1".
The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
When writing to a reserved space, set to "0". When reading, its content is indeterminate.
7
G
N
1
o
o r
0 -
. v
u
1
0
p
0
, 1
0
2
0
0
5
Page 14
f o
3
3
0
2. Central Processing Unit (CPU)