M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 201

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
Figure 16.10 Transmit and Receive Operation
0
C
1
9
8 /
0 .
B
(1) Transmit Timing (Internal clock selected)
Transfer Clock
TE bit in the UiC1
register
TI bit in the UiC1
register
CTSi
CLKi
TxDi
TXEPT bit in
the UiC0 register
IR bit in the SiTIC
register
0
0
The above applies under the following conditions:
0
2
• The CKDIR bit in the UiMR register is set to "0" (internal clock selected)
• The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled)
• The CKPOL bit the in UiC
• The UiIRS bit in the UiC
IR bit in the SiRIC
register
OER bit in the
UiRB register
RE bit in the UiC1
register
CLKi
RxDi
TE bit in the UiC1
register
TI bit in the UiC1
register
RTSi
RI bit in the UiC1
register
(2) Receive Timing (External clock selected)
G
The CRS bit is set to "0" (CTS function selected)
falling edge of the transfer clock)
f
7
The above applies under the following conditions:
N
EXT
1
• The CKDIR bit in the UiMR register is set to "1" (external clock selected)
• The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled)
• The CKPOL bit in the UiC0 register is set to "0"
o
o r
The CRS bit is set to "1" (RTS function selected)
(Data is received on the rising edge of the transfer clock)
0 -
: External clock frequency
. v
u
1
0
p
0
, 1
0
2
0
"H"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"L"
0
5
"H"
"1"
"0"
"1"
"0"
"1"
"0"
"L"
"1"
"0"
"1"
"0"
"1"
"0"
Page 180
1
Data is set in the UiTB register
Date is transferred from the UARTi
receive register to the UiRB register
0
register is set to "0" (no data in the UiTB register)
register is set to "0" (data transmitted on the
D
0
i=0 to 4
Data is transferred from the UiTB register to the UARTi transmit register
D
1
D
0
T
D
f o
CLK
2
D
1
3
D
3
3
D
2
0
D
Dummy data is set in the UiTB register
Tc
4
D
3
D
5
D
4
1 / f
D
Received data is taken in
6
D
5
EXT
D
Set to "0" by an interrupt request acknowledgement or by program
Set to "0" by an interrupt request acknowledgement or by program
7
D
Pulse stops because an "H"
signal is applied to CTSi
6
Data is transferred from the UiTB register to the UARTi transmit register
D
7
D
0
D
1
D
0
Read by the UiRB register
D
2
D
An "L" signal is applied when
the UiRB register is read
T
NOTE:
1
D
C
3
=T
1. The CNT3 to CNT0 bits in the TCSPR register select no division (
D
fj: Count source frequency set in the UiBRG register (f
m: Setting value of the UiBRG register
i = 0 to 4
2
n=0) or divide-by-2n (n=1 to 15).
D
CLK
Meet the following conditions while an "H" signal is applied to
the CLKi pin before receiving data:
4
D
• Set the TE bit in the UiC
• Set the RE bit in the UiC
• Write dummy data to the UiTB register
3
D
=2(m+1)/fj
5
D
16. Serial I/O (Clock Synchronous Serial I/O)
4
D
6
D
5
D
7
D
6
Pulse stops because the TE bit is set to "0"
D
7
D
0
D
0
D
1
1
1
D
register to "1" (transmit enable)
register to "1" (receive enable)
1
D
2
D
2
D
3
D
3
D
4
D
4
D
5
D
5
D
6
D
6
D
1
7
, f
8
, f
2n (1)
)