M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 80
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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M
R
R
e
E
3
. v
J
2
Figure 8.3 CM1 Register
0
C
1
9
8 /
0 .
B
0
0
0
2
G
7
N
1
o r
o
0 -
. v
System Clock Control Register 1
u
b7
1
NOTES:
p
0
0
, 1
0
b6
0
1. Rewrite the CM1 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. When the CM10 bit is set to "1", the clock applied to X
3. When the CM10 bit is set to "1", the MCD4 to MCD0 bits in the MCD register are set to "01000
4. The CM17 bit setting is enabled only when the CM21 bit in the CM2 register is set to "0". Use the
5. If the PM21 bit in the PM2 register is set to "1" (clock change disabled), the CM10 and CM17 bits do
2
resistor is disabled. X
(divide-by-8 mode). When the CM20 bit is set to "1" (oscillation stop detect function enabled) or the
CM21 bit to "1" (on-chip oscillator selected), do not set the CM10 bit to "1".
procedure shown in Figure 8.12 to set the CM17 bit to "1".
not change when written.
source), the CM10 bit setting does not change when written.
If the PM22 bit in the PM2 register is set to "1" (on-chip oscillator clock as watchdog timer count
0
b5
1
0
5
b4
0
Page 59
b3
0
b2
0
b1
0
b0
f o
IN
3
(b4 - b1)
Symbol
, X
3
CM10
CM17
(b5)
(b6)
0
Bit
CIN
Symbol
CM1
and X
All Clock Stop Control
Bit
Reserved Bit
Reserved Bit
Reserved Bit
CPU Clock Select
Bit 1
(2, 5)
COUT
(4,5)
Bit Name
are placed in high-impedance states.
(1)
Address
0007
16
OUT
becomes "H" and the built-in feedback
0: Clock oscillates
1: All clocks stop (stop mode)
Set to "0"
Set to "1"
Set to "0"
0: Main clock
1: PLL clock
After Reset
0010 0000
Function
2
8. Clock Generation Circuit
(3)
2
"
RW
RW
RW
RW
RW
RW
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