ST72F325K4T6 STMicroelectronics, ST72F325K4T6 Datasheet - Page 27

• Manufacturer Part Number: ST72F325K4T6
• Description: MCU 8BIT 16KB FLASH/ROM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F325K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7232X-SK/RAIS, ST72325-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5605

6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in
For more details, refer to dedicated parametric
section.
Main features
■
■
■
■
Figure 13. Clock, Reset and Supply Block Diagram
– 5 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
– Clock Security System (CSS) with Clock Filter
Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
Reset Sequence Manager (RSM)
Multi-Oscillator Clock Management (MO)
System Integrity Management (SI)
RESET
OSC2
OSC1
capability for monitoring the main supply
and Backup Safe Oscillator (enabled by op-
tion byte)
V
EVD
V
SS
DD
Figure
OSCILLATOR
RESET SEQUENCE
MULTI-
(MO)
MANAGER
(RSM)
13.
f
OSC
(option)
PLL
f
OSC2
SICSR
AVD AVD AVD LVD
SYSTEM INTEGRITY MANAGEMENT
S
0
1
CLOCK SECURITY SYSTEM
IE
CLOCK
FILTER
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 154.
Figure 12. PLL Block Diagram
f
OSC
AVD Interrupt Request
AUXILIARY VOLTAGE
F
LOW VOLTAGE
(CSS)
RF
DETECTOR
DETECTOR
(AVD)
(LVD)
0
SAFE
OSC
PLL x 2
CSS
IE
CSS Interrupt Request
/ 2
OSC2 =
CSS
D
WDG
f
RF
OSC2
f
OSC
PLL OPTION BIT
/2.
CLOCK (MCC/RTC)
WITH REALTIME
0
1
TIMER (WDG)
CONTROLLER
MAIN CLOCK
WATCHDOG
OSC2
ST72325xx
f
OSC2
of 4 to 8
27/197
f
CPU