PIC16F818-I/P Microchip Technology, PIC16F818-I/P Datasheet - Page 117

• Manufacturer Part Number: PIC16F818-I/P
• Description: IC MCU FLASH 1KX14 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F818-I/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.5
7.6
1997 Microchip Technology Inc.
Reading the EEPROM Data Memory
Writing to the EEPROM Data Memory
To read a data memory location, the user must write the address to the EEADR register and then
set control bit RD (EECON1<0>). The data is available, in the very next instruction cycle, in the
EEDATA register; therefore it can be read by the next instruction. EEDATA will hold this value until
another read or until it is written to by the user (during a write operation).
Example 7-1: Data EEPROM Read
To write an EEPROM data location, the user must first write the address to the EEADR register
and the data to the EEDATA register. Then the user must follow a specific sequence to initiate the
write for each byte.
Example 7-2: Data EEPROM Write
The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2,
write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be
disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents
accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost pro-
grams). The user should keep the WREN bit clear at all times, except when updating EEPROM.
The WREN bit is not cleared by hardware
After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle.
The WR bit will be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must
be cleared by software.
Sequence
Required
BCF
MOVLW
MOVWF
BSF
BSF
BCF
MOVF
STATUS, RP0
CONFIG_ADDR
EEADR
STATUS, RP0
EECON1, RD
STATUS, RP0
EEDATA, W
BSF
BCF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
Section 7. Data EEPROM
; Bank0
; Any location in Data EEPROM memory space
; Address to read
; Bank1
; EE Read
; Bank0
; W = EEDATA
STATUS, RP0
INTCON, GIE
EECON1, WREN ; Enable Write
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON, GIE
; Bank1
; Disable INTs.
;
; 55h must be written to EECON2
;
; Write AAh
; Set WR bit begin write
; Enable INTs.
to start write sequence
DS31007A-page 7-5
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