PIC16F818-I/P Microchip Technology, PIC16F818-I/P Datasheet - Page 355

• Manufacturer Part Number: PIC16F818-I/P
• Description: IC MCU FLASH 1KX14 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F818-I/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.6
18.6.1
PIR
RCSTA
TXREG
PIE
TXSTA
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'.
Note 1: The position of this bit is device dependent.
Name
1997 Microchip Technology Inc.
Shaded cells are not used for Synchronous Slave Transmission.
USART Synchronous Slave Transmit
USART Synchronous Slave Mode
CSRC
SPEN
Bit 7
TX7
Synchronous slave mode differs from the Master mode in the fact that the shift clock is supplied
externally at the TX/CK pin (instead of being supplied internally in master mode). This allows the
device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing the
CSRC bit (TXSTA<7>).
The operation of the synchronous master and slave modes are identical except in the case of the
SLEEP mode.
If two words are written to the TXREG and then the SLEEP instruction is executed, the following
will occur:
a)
b)
c)
d)
e)
Steps to follow when setting up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
Table 18-10: Registers Associated with Synchronous Slave Transmission
Bit 6
RX9
TX6
TX9
The first word will immediately transfer to the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF flag bit will not be set.
When the first word has been shifted out of TSR, the TXREG register will transfer the sec-
ond word to the TSR and the TXIF flag bit will now be set.
If the TXIE enable bit is set, the interrupt will wake the chip from SLEEP and if the global
interrupt is enabled, the program will branch to the interrupt vector (0004h).
Enable the synchronous slave serial port by setting the SYNC and SPEN bits and clearing
the CSRC bit.
Clear the CREN and SREN bits.
If interrupts are desired, then set the TXIE enable bit.
If 9-bit transmission is desired, then set the TX9 bit.
Enable the transmission by setting the TXEN enable bit.
If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D bit.
Start transmission by loading data to the TXREG register.
SREN CREN
TXEN SYNC
Bit 5
TX5
Bit 4
TX4
TXIE
TXIF
Bit 3
TX3
—
—
(1)
(1)
BRGH
FERR
Bit 2
TX2
Section 18. USART
OERR
TRMT
Bit 1
TX1
RX9D
TX9D
Bit 0
TX0
0000 -00x
0000 0000
0000 -010
0000 0000
Value on:
POR,
BOR
0
0
DS31018A-page 18-19
other Resets
Value on all
0000 -00x
0000 0000
0000 -010
0000 0000
0
0
18