PIC16F818-I/P Microchip Technology, PIC16F818-I/P Datasheet - Page 347

• Manufacturer Part Number: PIC16F818-I/P
• Description: IC MCU FLASH 1KX14 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F818-I/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.4.2
1997 Microchip Technology Inc.
RX/DT
USART Asynchronous Receiver
Baud Rate Generator
x64 Baud Rate CLK
SPBRG
Pin Buffer
and Control
The receiver block diagram is shown in
drives the data recovery block. The data recovery block is actually a high speed shifter operating
at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at
F
Once Asynchronous mode is selected, reception is enabled by setting the CREN bit
(RCSTA<4>).
The heart of the receiver is the receive (serial) shift register (RSR). After sampling the RX/TX pin
for the STOP bit, the received data in the RSR is transferred to the RCREG register (if it is empty).
If the transfer is complete, the RCIF flag bit is set. The actual interrupt can be enabled/disabled
by setting/clearing the RCIE enable bit. The RCIF flag bit is a read only bit which is cleared by
the hardware. It is cleared when the RCREG register has been read and is empty. The RCREG
is a double buffered register, i.e. it is a two deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR register.
On the detection of the STOP bit of the third byte, if the RCREG register is still full then overrun
error bit, OERR (RCSTA<1>), will be set. The word in the RSR will be lost. The RCREG register
can be read twice to retrieve the two bytes in the FIFO. The OERR bit has to be cleared in soft-
ware. This is done by resetting the receive logic (the CREN bit is cleared and then set). If the
OERR bit is set, transfers from the RSR register to the RCREG register are inhibited, so it is
essential to clear the OERR bit if it is set. Framing error bit, FERR (RCSTA<2>), is set if a stop
bit is detected as a low level. The FERR bit and the 9th receive bit are buffered the same way as
the receive data. Reading the RCREG will load the RX9D and FERR bits with new values, there-
fore it is essential for the user to read the RCSTA register before reading the next RCREG reg-
ister in order not to lose the old (previous) information in the FERR and RX9D bits.
Figure 18-4:
SPEN
OSC
.
USART Receive Block Diagram
Data
Recovery
Interrupt
CREN
Figure
RCIF
RCIE
RX9
Section 18. USART
18-4. The data is received on the RX/DT pin and
MSb
Stop
RX9D
(8)
OERR
7
RSR register
RCREG register
8
Data Bus
DS31018A-page 18-11
1
FERR
0
Start
LSb
FIFO
18