ATTINY861-15MZ Atmel, ATTINY861-15MZ Datasheet - Page 121

• Manufacturer Part Number: ATTINY861-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY861-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.11.6
16.11.7
16.11.8
2588B–AVR–11/06
TCNT1 – Timer/Counter1
TC1H – Timer/Counter1 High Byte
OCR1A – Timer/Counter1 Output Compare Register A
the Output Compare Override Enable Bit is cleared.
Override Enable Bits and their corresponding Output Compare pins.
Table 16-20. Output Compare Override Enable Bits vs. Output Compare Pins
This 8-bit register contains the value of Timer/Counter1.
The Timer/Counter1 is realized as a 10-bit up/down counter with read and write access. Due to
synchronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one
and half CPU clock cycles in synchronous mode and at most one CPU clock cycles for asyn-
chronous mode. When a 10-bit accuracy is preferred, special procedures must be followed for
accessing the 10-bit TCNT1 register via the 8-bit AVR data bus. These procedures are
described in section
can be used as an 8-bit Timer/Counter. Note that the Timer/Counter1 always starts counting up
after writing the TCNT1 register.
The temporary Timer/Counter1 register is an 2-bit read/write register.
• Bits 7:2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny261/461/861 and always reads as zero.
• Bits 1:0 - TC19, TC18: Two MSB bits of the 10-bit accesses
If 10-bit accuracy is used, the Timer/Counter1 High Byte Register (TC1H) is used for temporary
storing the MSB bits (TC19, TC18) of the 10-bit acceses. The same TC1H register is shared
between all 10-bit registers within the Timer/Counter1. Note that special procedures must be fol-
lowed when accessing the 10-bit TCNT1 register via the 8-bit AVR data bus. These procedures
are described in section
The output compare register A is an 8-bit read/write register.
OC1OE0
OC1A
Bit
0x2E (0x4E)
Read/Write
Initial value
Bit
0x25 (0x45)
Read/Write
Initial value
Bit
0x2D (0x4D)
Read/Write
Initial value
(PB0)
MSB
MSB
R/W
R/W
OC1OE1
OC1A
R
7
0
7
0
7
0
-
”Accessing 10-Bit Registers” on page
(PB1)
”Accessing 10-Bit Registers” on page
R/W
R/W
R
6
0
6
0
6
0
-
OC1OE2
OC1B
R/W
R/W
R
5
0
5
0
5
0
-
(PB2)
R/W
R/W
R
4
0
4
0
4
0
-
OC1OE3
OC1B
R/W
R/W
R
3
0
3
0
3
0
-
Table 16-20
(PB3)
110. Alternatively the Timer/Counter1
ATtiny261/461/861
R/W
R/W
110.
R
2
0
2
0
2
0
-
OC1OE4
OC1D
shows the Output Compare
TC19
(PB4)
R/W
R/W
R/W
1
0
1
0
1
0
TC18
LSB
LSB
R/W
R/W
R/W
OC1OE5
OC1D
0
0
0
0
0
0
(PB5)
OCR1A
TCNT1
TC1H
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