ATTINY861-15MZ Atmel, ATTINY861-15MZ Datasheet - Page 27

• Manufacturer Part Number: ATTINY861-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY861-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5
2588B–AVR–11/06
High Frequency PLL Clock - PLL
Figure 7-3.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table
Table 7-3.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to
31
There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator
for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as
a system clock source, by programming the CKSEL fuses to ‘0001’, it is divided by four like
shown in
SUT fuses as shown in
Table 7-4.
Table 7-5.
SUT1..0
SUT1..0
for details.
00
01
10
11
00
01
10
11
7-3.
Table
CKSEL3..0
Start-up Time from Power-
Start-up Time from Power
External Clock Drive Configuration
Start-up Times for the External Clock Selection
PLLCK Operating Modes
Start-up Times for the PLLCK
7-4. When this clock source is selected, start-up times are determined by the
0001
down and Power-save
16K (16384) + 64 ms
16K (16384) + 4 ms
1K (1024) + 64 ms
1K (1024) + 4 ms
CLK
Table
Down
6 CK
6 CK
6 CK
EXTERNAL
7-5. See also
SIGNAL
CLOCK
”PCK Clocking System” on page
Additional Delay from
Additional Delay from
Reset (V
Reserved
14CK + 64 ms
14CK + 4 ms
14CK + 4 ms
14CK + 4 ms
14CK + 4 ms
14CK + 4 ms
CLKI
GND
Reset
14CK
CC
Nominal Frequency
= 5.0V)
ATtiny261/461/861
”System Clock Prescaler” on page
16 MHz
Recommended usage
BOD enabled
Fast rising power
BOD enabled
Fast rising power
Slowly rising power
Slowly rising power
Slowly rising power
Recommended Usage
25.
27