ATTINY861-15MZ Atmel, ATTINY861-15MZ Datasheet - Page 43
![MCU AVR 8K FLASH 15MHZ 32-QFN](/photos/30/99/309943/qfn-32_sml.jpg)
ATTINY861-15MZ
Manufacturer Part Number
ATTINY861-15MZ
Description
MCU AVR 8K FLASH 15MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY861-15MZ.pdf
(236 pages)
Specifications of ATTINY861-15MZ
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
16
Eeprom Size
512 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
512 x 8
Program Memory Size
8KB (8K x 8)
Data Converters
A/D 11x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY861-15MZ
Manufacturer:
ATMEL
Quantity:
1 465
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9.3
9.3.1
9.3.2
2588B–AVR–11/06
Timed Sequences for Changing the Configuration of the Watchdog Timer
Safety Level 1
Safety Level 2
Table 9-1.
Figure 9-7.
The sequence for changing configuration differs slightly between the two safety levels. Separate
procedures are described for each level.
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to one without any restriction. A timed sequence is needed when disabling an enabled Watch-
dog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written
2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,
WDTON
Unprogrammed
Programmed
to WDE regardless of the previous value of the WDE bit.
desired, but with the WDCE bit cleared.
always is set, the WDE must be written to one to start the timed sequence.
but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
WDT Configuration as a Function of the Fuse Settings of WDTON
Watchdog Timer
Safety
Level
1
2
WATCHDOG
OSCILLATOR
RESET
128 kHz
WDP0
WDP1
WDP2
WDP3
WDE
WDT Initial
State
Disabled
Enabled
How to Disable the
WDT
Timed sequence
Always enabled
MCU RESET
PRESCALER
WATCHDOG
ATtiny261/461/861
How to Change Time-
out
No limitations
Timed sequence
43
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