ATTINY861-15MZ Atmel, ATTINY861-15MZ Datasheet - Page 24

• Manufacturer Part Number: ATTINY861-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY861-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7. System Clock and Clock Options
7.1
7.1.1
7.1.2
7.1.3
7.1.4
24
Clock Systems and their Distribution
ATtiny261/461/861
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
ADC Clock – clk
I/O
Figure 7-1
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 7-1.
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is
also used by the External Interrupt module, but note that some external interrupts are detected
by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
CPU
ADC
FLASH
presents the principal clock systems in the AVR and their distribution. All of the clocks
Clock Distribution
34. The clock systems are detailed below.
”Power Manage-
2588B–AVR–11/06