ATTINY861-15MZ Atmel, ATTINY861-15MZ Datasheet - Page 21

• Manufacturer Part Number: ATTINY861-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY861-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.4
6.4.1
6.5
6.5.1
2588B–AVR–11/06
I/O Memory
Register Description
General Purpose I/O Registers
EEARH and EEARL – EEPROM Address Register
The I/O space definition of the ATtiny261/461/861 is shown in
All ATtiny261/461/861 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
instruction set section for more details. When using the I/O specific commands IN and OUT, the
I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using
LD and ST instructions, 0x20 must be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and Peripherals Control Registers are explained in later sections.
The ATtiny261/461/861 contains three General Purpose I/O Registers. These registers can be
used for storing any information, and they are particularly useful for storing global variables and
Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly
bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
• Bit 7:1 – Res6:0: Reserved Bits
These bits are reserved for future use and will always read as 0 in ATtiny261/461/861.
• Bits 8:0 – EEAR8:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL – specifies the high EEPROM address
in the 128/256/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 127/255/511. The initial value of EEAR is undefined. A proper value must be writ-
ten before the EEPROM may be accessed.
Bit
0x1F (0x3F)
0x1E (0x3E)
Bit
Read/Write
Read/Write
Initial Value
Initial Value
EEAR7
R/W
R
7
7
0
X
-
EEAR6
R/W
R
6
6
0
X
-
EEAR5
R/W
R
5
5
0
X
-
EEAR4
R/W
R
4
4
0
X
-
EEAR3
R/W
R
3
3
0
X
-
EEAR2
ATtiny261/461/861
R/W
”Register Summary” on page
R
2
2
0
X
-
EEAR1
R/W
R
1
1
0
X
-
EEAR8
EEAR0
R/W
R/W
0
0
X
X
EEARH
EEARL
218.
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