ATTINY861-15MZ Atmel, ATTINY861-15MZ Datasheet - Page 124

• Manufacturer Part Number: ATTINY861-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY861-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.11.13 TIFR – Timer/Counter1 Interrupt Flag Register
16.11.14 DT1 – Timer/Counter1 Dead Time Value
124
ATtiny261/461/861
• Bit 7- OCF1D: Output Compare Flag 1D
The OCF1D bit is set (one) when compare match occurs between Timer/Counter1 and the data
value in OCR1D - Output Compare Register 1D. OCF1D is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF1D is cleared, after synchroniza-
tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1D, and OCF1D
are set (one), the Timer/Counter1 D compare match interrupt is executed.
• Bit 6 - OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data
value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchroniza-
tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A
are set (one), the Timer/Counter1 A compare match interrupt is executed.
• Bit 5 - OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data
value in OCR1B - Output Compare Register 1A. OCF1B is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchroniza-
tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B
are set (one), the Timer/Counter1 B compare match interrupt is executed.
• Bit 2 - TOV1: Timer/Counter1 Overflow Flag
In Normal Mode and Fast PWM Mode the TOV1 bit is set (one) each time the counter reaches
TOP at the same clock cycle when the counter is reset to BOTTOM. In Phase and Frequency
Correct PWM Mode the TOV1 bit is set (one) each time the counter reaches BOTTOM at the
same clock cycle when zero is clocked to the counter.
The bit TOV1 is cleared by hardware when executing the corresponding interrupt handling vec-
tor. Alternatively, TOV1 is cleared, after synchronization clock cycle, by writing a logical one to
the flag. When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and
TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.
The dead time value register is an 8-bit read/write register.
The dead time delay of all Timer/Counter1 channels are adjusted by the dead time value regis-
ter, DT1. The register consists of two fields, DT1H3..0 and DT1L3..0, one for each
complementary output. Therefore a different dead time delay can be adjusted for the rising edge
of OC1x and the rising edge of OC1x.
Bit
0x24 (0x44)
Read/Write
Initial value
Bit
0x38 (0x58)
Read/Write
Initial value
OCF1D
DT1H3
R/W
R/W
7
0
7
0
OCF1A
DT1H2
R/W
R/W
6
0
6
0
OCF1B
DT1H1
R/W
R/W
5
0
5
0
OCF0A
DT1H0
R/W
R/W
4
0
4
0
OCF0B
DT1L3
R/W
R/W
3
0
3
0
DT1L2
TOV1
R/W
R/W
2
0
2
0
DT1L1
TOV0
R/W
R/W
1
0
1
0
DT1L0
ICF0
R/W
R/W
0
0
0
0
2588B–AVR–11/06
TIFR
DT1