PIC18F65K22-I/MRRSL Microchip Technology, PIC18F65K22-I/MRRSL Datasheet - Page 116

• Manufacturer Part Number: PIC18F65K22-I/MRRSL
• Description: MCU PIC 32K FLASH MEM XLP 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K22-I/MRRSL

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Controller Family/series: PIC18
• No. Of I/o's: 53
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
7.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Write 0xAA to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. Re-enable the interrupts.
13. Verify the memory (table read).
DS39960B-page 116
Read the 64 or 128 bytes into RAM.
Update the data values in RAM as necessary.
Load the Table Pointer register with the address
being erased.
Execute the row erase procedure.
Load the Table Pointer register with the address
of the first byte being written.
Write the 64 or 128 bytes into the holding
registers with auto-increment.
Set the EECON1 register for the write operation:
• Set the EEPGD bit to point to program memory
• Clear the CFGS bit to access program memory
• Set the WREN to enable byte writes
Disable the interrupts.
Write 0x55 to EECON2.
The CPU will stall for duration of the write for T
(see parameter D133A).
FLASH PROGRAM MEMORY WRITE
SEQUENCE
IW
Preliminary
An example of the required code is shown in
Example 7-3 on the following page.
Note:
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 or
128 bytes in the holding register.
Self-write
EEPROM memory cannot be done while
running in LP Oscillator mode (Low-Power
mode). Therefore, executing a self-write
will put the device into High-Power mode.
 2010 Microchip Technology Inc.
execution
to
Flash
and