PIC18F65K22-I/MRRSL Microchip Technology, PIC18F65K22-I/MRRSL Datasheet - Page 137

MCU PIC 32K FLASH MEM XLP 64QFN

PIC18F65K22-I/MRRSL

Manufacturer Part Number
PIC18F65K22-I/MRRSL
Description
MCU PIC 32K FLASH MEM XLP 64QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F65K22-I/MRRSL

Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC18
No. Of I/o's
53
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
64MHz
No. Of Timers
8
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
10.0
10.1
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows PIC18 devices to be used in many applications
previously reserved for digital-signal processors. A
comparison of various hardware and software multiply
operations, along with the savings in memory and
execution time, is shown in Table 10-1.
10.2
Example 10-1 shows the instruction sequence for an 8 x
8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded in
the WREG register.
Example 10-2 shows the sequence to do an 8 x 8
signed multiplication. To account for the sign bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
TABLE 10-1:
 2010 Microchip Technology Inc.
8 x 8 unsigned
16 x 16 signed
8 x 8 signed
unsigned
Routine
16 x 16
8 x 8 HARDWARE MULTIPLIER
Introduction
Operation
Without hardware multiply
Without hardware multiply
Without hardware multiply
Without hardware multiply
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Multiply Method
Program
Memory
(Words)
13
33
21
28
52
35
1
6
Preliminary
Cycles
(Max)
242
254
69
91
28
40
1
6
PIC18F87K22 FAMILY
EXAMPLE 10-1:
EXAMPLE 10-2:
MOVF
MULWF
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
@ 64 MHz
15.1 s
15.8 s
62.5 ns
375 ns
4.3 s
5.6 s
1.7 s
2.5 s
ARG1, W
ARG2
ARG1, W
ARG2
ARG2, SB
PRODH, F
ARG2, W
ARG1, SB
PRODH, F
@ 48 MHz
83.3 ns
20.1 s
21.2 s
500 ns
5.7 s
7.5 s
2.3 s
3.3 s
8 x 8 UNSIGNED MULTIPLY
ROUTINE
8 x 8 SIGNED MULTIPLY
ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
; Test Sign Bit
; PRODH = PRODH
;
Time
@ 10 MHz
101.6 s
27.6 s
36.4 s
96.8 s
11.2 s
16.0 s
400 ns
2.4 s
DS39960B-page 137
- ARG1
- ARG2
@ 4 MHz
242 s
254 s
69 s
91 s
28 s
40 s
1 s
6 s

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