PIC18F65K22-I/MRRSL Microchip Technology, PIC18F65K22-I/MRRSL Datasheet - Page 347
![MCU PIC 32K FLASH MEM XLP 64QFN](/photos/19/6/190652/4732178_sml.jpg)
PIC18F65K22-I/MRRSL
Manufacturer Part Number
PIC18F65K22-I/MRRSL
Description
MCU PIC 32K FLASH MEM XLP 64QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F65K22T-IPTRSL.pdf
(548 pages)
3.PIC18F65K22T-IPTRSL.pdf
(10 pages)
Specifications of PIC18F65K22-I/MRRSL
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC18
No. Of I/o's
53
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
64MHz
No. Of Timers
8
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F722-ISS PDF datasheet
- PIC18F65K22T-IPTRSL PDF datasheet #2
- PIC18F65K22T-IPTRSL PDF datasheet #3
- Current page: 347 of 548
- Download datasheet (5Mb)
22.4
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
22.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
TABLE 22-9:
2010 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTA1
TXREG1
TXSTA1
BAUDCON1
SPBRGH1
SPBRG1
RCSTA2
TXREG2
TXSTA2
BAUDCON2
SPBRGH2
SPBRG2
ODCON3
PMD0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREGx
register.
Flag bit, TXxIF, will not be set.
When the first word has been shifted out of TSR,
the TXREGx register will transfer the second word
to the TSR and flag bit, TXxIF, will now be set.
Name
EUSART Synchronous
Slave Mode
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
EUSART1 Transmit Register
EUSART2 Transmit Register
EUSART1 Baud Rate Generator Register High Byte
EUSART1 Baud Rate Generator Register
EUSART2 Baud Rate Generator Register High Byte
EUSART2 Baud Rate Generator Register
GIE/GIEH
TMR5GIF
TMR5GIE
TMR5GIP
ABDOVF
ABDOVF
CCP3MD
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
PSPIE
PSPIP
PSPIF
CSRC
CSRC
U2OD
SPEN
SPEN
Bit 7
PEIE/GIEL
CCP2MD
RCIDL
RCIDL
U1OD
ADIF
ADIE
ADIP
Bit 6
RX9
RX9
TX9
TX9
—
—
—
CCP1MD UART2MD UART1MD
TMR0IE
RXDTP
RXDTP
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SREN
TXEN
TXEN
Bit 5
—
Preliminary
TXCKP
TXCKP
INT0IE
CREN
CREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
SYNC
SYNC
Bit 4
—
PIC18F87K22 FAMILY
e)
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
If enable bit, TXxIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Clear bits, CREN and SREN.
If interrupts are desired, set enable bit, TXxIE.
If 9-bit transmission is desired, set bit, TX9.
Enable the transmission by setting enable bit,
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
CTMUIE
CTMUIP
CTMUIF
SSP1IF
SSP1IE
SSP1IP
ADDEN
SENDB
ADDEN
SENDB
BRG16
BRG16
RBIE
Bit 3
—
TMR1GIE
TMR1GIP
TMR1GIF
SSP2MD
TMR0IF
CCP2IE
CCP2IP
CCP2IF
BRGH
BRGH
FERR
FERR
Bit 2
—
—
—
SSP1MD
TMR2IF
TMR2IE
TMR2IP
CCP1IE
CCP1IP
CCP1IF
INT0IF
OERR
OERR
TRMT
TRMT
WUE
WUE
Bit 1
—
DS39960B-page 347
CTMUDS
RTCCIE
RTCCIP
TMR1IF
TMR1IE
TMR1IP
RTCCIF
ADCMD
ABDEN
ABDEN
RX9D
RX9D
TX9D
TX9D
RBIF
Bit 0
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