PIC18F65K22-I/MRRSL Microchip Technology, PIC18F65K22-I/MRRSL Datasheet - Page 169

• Manufacturer Part Number: PIC18F65K22-I/MRRSL
• Description: MCU PIC 32K FLASH MEM XLP 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K22-I/MRRSL

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Controller Family/series: PIC18
• No. Of I/o's: 53
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 12-1:
TABLE 12-2:
 2010 Microchip Technology Inc.
RA0/AN0/ULPWU
RA1/AN1
RA2/AN2/V
RA3/AN3/V
RA4/T0CKI
RA5/AN4/T1CKI/
T3G/HLVDIN
OSC2/CLKO/RA6
OSC1/CLKI/RA7
Legend:
PORTA
LATA
TRISA
ANCON0
Legend:
Note 1:
Name
Pin Name
REF
REF
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
— = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are
disabled and read as ‘x’.
-
+
TRISA7
LATA7
ANSEL7
RA7
Bit 7
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
PORTA FUNCTIONS
(1)
Function
ULPWU
HLVDIN
(1)
V
T0CKI
T1CKI
OSC2
CLKO
OSC1
(1)
V
CLKI
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
RA4
RA5
AN4
T3G
RA6
RA7
REF
REF
+
-
TRISA6
LATA6
ANSEL6
RA6
Bit 6
Setting
TRIS
(1)
0
1
1
1
0
1
1
0
1
1
1
0
1
1
1
0
1
x
0
1
1
x
x
1
x
x
0
1
x
x
0
1
(1)
(1)
I/O
ANSEL5
O
O
O
O
O
O
O
O
O
O
TRISA5
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LATA5
Bit 5
RA5
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
TTL
I/O
ST
ST
ST
ST
Preliminary
ANSEL4
TRISA4
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
Ultra low-power wake-up input.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
LATA<2> data output; not affected by analog input.
PORTA<2> data input; disabled when analog functions are enabled.
A/D Input Channel 2. Default input configuration on POR.
A/D and comparator low reference voltage input.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input is enabled.
A/D Input Channel 3. Default input configuration on POR.
A/D and comparator high reference voltage input.
LATA<4> data output.
PORTA<4> data input. Default configuration on POR.
Timer0 clock input.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D Input Channel 4. Default configuration on POR.
Timer1 Clock Input.
Timer3 External clock gate input.
High/Low-Voltage Detect external trip point input.
Main oscillator feedback output connection (HS, XT and LP modes).
System cycle clock output (F
LATA<6> data output; disabled when FOSC2 Configuration bit is set.
PORTA<6> data input; disabled when FOSC2 Configuration bit is set.
Main oscillator input connection (HS, XT and LP modes).
Main external clock source input (EC modes).
LATA<7> data output; disabled when FOSC2 Configuration bit is set.
PORTA<7> data input; disabled when FOSC2 Configuration bit is set.
LATA4
Bit 4
RA4
PIC18F87K22 FAMILY
ANSEL3
TRISA3
LATA3
Bit 3
RA3
Description
OSC
ANSEL2
TRISA2
LATA2
Bit 2
RA2
/4) (EC and INTOSC modes).
ANSEL1
TRISA1
LATA1
Bit 1
RA1
DS39960B-page 169
ANSEL0
TRISA0
LATA0
Bit 0
RA0