PIC18F65K22-I/MRRSL Microchip Technology, PIC18F65K22-I/MRRSL Datasheet - Page 262

MCU PIC 32K FLASH MEM XLP 64QFN

PIC18F65K22-I/MRRSL

Manufacturer Part Number
PIC18F65K22-I/MRRSL
Description
MCU PIC 32K FLASH MEM XLP 64QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F65K22-I/MRRSL

Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC18
No. Of I/o's
53
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
64MHz
No. Of Timers
8
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F87K22 FAMILY
20.3
In Compare mode, the 16-bit CCPRx register value is
constantly compared against the Timer register pair
value selected in the CCPTMR1 register. When a
match occurs, the ECCPx pin can be:
• Driven high
• Driven low
• Toggled (high-to-low or low-to-high)
• Unchanged (that is, reflecting the state of the I/O
The action on the pin is based on the value of the mode
select bits (CCPxM<3:0>). At the same time, the
interrupt flag bit, CCPxIF, is set.
20.3.1
Users must configure the ECCPx pin as an output by
clearing the appropriate TRIS bit.
FIGURE 20-2:
DS39960B-page 262
latch)
Note:
Compare Mode
ECCP PIN CONFIGURATION
Clearing the CCPxCON register will force
the ECCPx compare output latch (depend-
ing on device configuration) to the default
low level. This is not the PORTx I/O data
latch.
0
1
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR1H
TMR1H
TMR3H
C1TSEL0
C1TSEL1
C1TSEL2
Comparator
CCPR1L
TMR1L
TMR3L
Compare
Match
Preliminary
Set CCP1IF
(Timer1/Timer3 Reset, A/D Trigger)
20.3.2
Timer1 2, 3, 4, 6, 8, 10 or 12 must be running in Timer
mode or Synchronized Counter mode if the ECCP
module is using the compare feature. In Asynchronous
Counter mode, the compare operation will not work
reliably.
20.3.3
When the Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the ECCPx pin is not affected;
only the CCPxIF interrupt flag is affected.
20.3.4
The ECCP module is equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the
(CCPxM<3:0> = 1011).
The Special Event Trigger resets the Timer register pair
for whichever timer resource is currently assigned as the
module’s time base. This allows the CCPRx registers to
serve as a programmable period register for either timer.
The Special Event Trigger can also start an A/D conver-
sion. In order to do this, the A/D Converter must
already be enabled.
Special Event Trigger
CCP1CON<3:0>
Compare
Output
Logic
4
TIMER1/2/3/4/6/8/10/12 MODE
SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Special
S
R
Q
 2010 Microchip Technology Inc.
Output Enable
Event
TRIS
ECCP1 Pin
Trigger
mode

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