P89LPC982FDH,529 NXP Semiconductors, P89LPC982FDH,529 Datasheet - Page 12

• Manufacturer Part Number: P89LPC982FDH,529
• Description: MCU 80C51 8KB FLASH 28TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC982FDH,529

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 5
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935290303529

NXP Semiconductors
Table 3.
P89LPC980_982_983_985
Product data sheet
Symbol
P1.7/AD04/T3EX/
MOSI
P2.0 to P2.7
P2.0/AD07/TXD
P2.1/AD06/RXD
P2.2/MOSI
P2.3/MISO
P2.4/SS
P2.5/SPICLK
P2.6/SCL
P2.7/SDA
P3.0 to P3.1
Pin description
Pin
PLCC28,
TSSOP28
4
1
2
13
14
15
16
27
28
…continued
Type Description
I/O
I
I
I/O
I/O
I/O
I
O
I/O
I
I
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P1.7 — Port 1 bit 7. High current source.
AD04 — ADC0 channel 4 analog input. (P89LPC985)
T3EX — Timer/counter 3 external capture input.
MOSI — SPI master out slave in. When configured as master, this pin is output;
when configured as slave, this pin is input. (pin remap)
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to
7.16.1 “Port configurations”
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0 — Port 2 bit 0.
AD07 — ADC0 channel 7 analog input. (P89LPC985)
TXD — Transmitter output for serial port. (pin remap)
P2.1 — Port 2 bit 1.
AD06 — ADC0 channel 6 analog input. (P89LPC985)
RXD — Receiver input for serial port. (pin remap)
P2.2 — Port 2 bit 2.
MOSI — SPI master out slave in. When configured as master, this pin is output;
when configured as slave, this pin is input.
P2.3 — Port 2 bit 3.
MISO — SPI master in slave out. When configured as master, this pin is input,
when configured as slave, this pin is output.
P2.4 — Port 2 bit 4.
SS — SPI Slave select.
P2.5 — Port 2 bit 5.
SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input.
P2.6 — Port 2 bit 6.
SCL — I
P2.7 — Port 2 bit 7.
SDA — I
Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 3 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to
7.16.1 “Port configurations”
All pins have Schmitt trigger inputs.
Port 3 also provides various special functions as described below:
2
2
C-bus serial clock input/output. (pin remap)
C-bus serial data input/output. (pin remap)
Rev. 4 — 15 June 2010
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC980/982/983/985
and
and
Table 13 “Static characteristics”
Table 13 “Static characteristics”
© NXP B.V. 2010. All rights reserved.
for details.
for details.
Section
Section
12 of 85