P89LPC982FDH,529 NXP Semiconductors, P89LPC982FDH,529 Datasheet - Page 62

• Manufacturer Part Number: P89LPC982FDH,529
• Description: MCU 80C51 8KB FLASH 28TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC982FDH,529

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 5
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935290303529

NXP Semiconductors
P89LPC980_982_983_985
Product data sheet
8.6 Boundary limits interrupt
8.7 Clock divider
8.8 Power-down and Idle mode
The ADC has both a high and low boundary limit register. The user may select whether an
interrupt is generated when the conversion result is within (or equal to) the high and low
boundary limits or when the conversion result is outside the boundary limits. An interrupt
will be generated, if enabled, if the result meets the selected interrupt criteria. The
boundary limit may be disabled by clearing the boundary limit interrupt enable.
An early detection mechanism exists when the interrupt criteria has been selected to be
outside the boundary limits. In this case, after the four MSBs have been converted, these
four bits are compared with the four MSBs of the boundary high and low registers. If the
four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)
an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt
criteria, the boundary limits will again be compared after all 8 MSBs have been converted.
A boundary status register (BNDSTA0) flags the channels which caused a boundary
interrupt.
The ADC requires that its internal clock source be in the range of 500 kHz to 6.6 MHz to
maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is
provided for this purpose.
In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit
Idle mode when the conversion is completed if the A/D interrupt is enabled. In
Power-down mode or Total Power-down mode, the ADC does not function. If the ADC is
enabled, they will consume power. Power can be reduced by disabling the ADC.
Rev. 4 — 15 June 2010
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC980/982/983/985
© NXP B.V. 2010. All rights reserved.
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