P89LPC982FDH,529 NXP Semiconductors, P89LPC982FDH,529 Datasheet - Page 35

• Manufacturer Part Number: P89LPC982FDH,529
• Description: MCU 80C51 8KB FLASH 28TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC982FDH,529

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 5
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935290303529

NXP Semiconductors
P89LPC980_982_983_985
Product data sheet
Fig 9.
(1) ±10 % at 400 kHz.
(7.3728 MHz/14.7456 MHz ± 1 %)
Block diagram of oscillator control
WITH CLOCK DOUBLER
XTAL1
XTAL2
RC OSCILLATOR
7.10 CCLK wake-up delay
7.12 Low power select
7.11 CCLK modification: DIVM register
(400 kHz/25 kHz)
OSCILLATOR
WATCHDOG
The P89LPC980/982/983/985 has an internal wake-up timer that delays the clock until it
stabilizes depending on the clock source used. If the clock source is any of the three
crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles
plus 60 μs to 100 μs. If the clock source is the internal RC oscillator, the delay is 200 μs to
300 μs. If the clock source is watchdog oscillator or external clock, the delay is
32 OSCCLK cycles.
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
The P89LPC980/982/983/985 is designed to run at 18 MHz (CCLK) maximum. However,
if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower
the power consumption further. On any reset, CLKLP is logic 0 allowing highest
performance access. This bit can then be set in software if CCLK is running at 8 MHz or
slower.
MEDIUM FREQUENCY
HIGH FREQUENCY
LOW FREQUENCY
(1)
RCCLK
TIMER 0 AND
TIMER 1
Rev. 4 — 15 June 2010
TIMER 2/
TIMER 3/
8-bit microcontroller with accelerated two-clock 80C51 core
TIMER 4
OSCCLK
PCLK
P89LPC980/982/983/985
DIVM
SPI
CCLK
PCLK
÷2
UART
(P89LPC983/985)
I
2
C-BUS
WDT
ADC
CPU
RTC
© NXP B.V. 2010. All rights reserved.
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