P89LPC982FDH,529 NXP Semiconductors, P89LPC982FDH,529 Datasheet - Page 75

• Manufacturer Part Number: P89LPC982FDH,529
• Description: MCU 80C51 8KB FLASH 28TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC982FDH,529

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 5
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935290303529

NXP Semiconductors
Table 16.
V
T
P89LPC980_982_983_985
Product data sheet
Symbol
t
t
t
VR
RH
RL
amb
Fig 27. SPI slave timing (CPHA = 1)
DD
= 2.4 V to 5.5 V, unless otherwise specified.
=
−
40
°
Dynamic characteristics, ISP entry mode
C to +85
Parameter
V
time
RST HIGH time
RST LOW time
(CPOL = 0)
(CPOL = 1)
DD
11.2 ISP entry mode
SPICLK
SPICLK
(output)
active to RST active delay
(input)
(input)
(input)
MISO
MOSI
t
SPIA
SS
°
C for industrial applications, unless otherwise specified.
Fig 28. ISP entry waveform
t
t
SPILEAD
t
SPIOH
SPIF
t
not defined
t
SPIF
SPIDV
V
t
RST
t
SPICLKH
SPICLKL
t
DD
SPIF
t
SPIDSU
slave MSB/LSB out
MSB/LSB in
T
SPICYC
Conditions
pin P1.5/RST
pin P1.5/RST
pin P1.5/RST
Rev. 4 — 15 June 2010
t
SPIOH
t
t
t
SPICLKL
SPICLKH
t
SPIDV
SPIDH
8-bit microcontroller with accelerated two-clock 80C51 core
t
SPIR
t
VR
t
RL
t
SPIR
t
RH
P89LPC980/982/983/985
t
SPIOH
t
SPIDV
Min
50
1
1
t
SPIDSU
slave LSB/MSB out
LSB/MSB in
Typ
-
-
-
t
t
SPIDH
SPILAG
002aaa911
002aaa912
t
SPIR
Max
-
32
-
© NXP B.V. 2010. All rights reserved.
t
SPIDIS
Unit
μs
μs
μs
75 of 85