P89LPC9402FBD,557 NXP Semiconductors, P89LPC9402FBD,557 Datasheet - Page 37

• Manufacturer Part Number: P89LPC9402FBD,557
• Description: IC 80C51 MCU FLASH 8K 64-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC9402FBD,557

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 64-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LED, POR, PWM, WDT
• Number Of I /o: 23
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935288631557

NXP Semiconductors
P89LPC9402_1
Product data sheet
Fig 16. Watchdog timer in Watchdog mode (WDTE = 1)
watchdog
oscillator
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed
PCLK
sequence.
7.26.1 Software reset
7.26.2 Dual data pointers
0
1
7.25 Watchdog timer
7.26 Additional features
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
oscillator
crystal
The watchdog timer causes a system reset when it underflows as a result of a failure to
feed the timer prior to the timer reaching its terminal count. It consists of a programmable
12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap
taken from the prescaler. The clock source for the prescaler can be the PCLK, the nominal
400 kHz watchdog oscillator or crystal oscillator. The watchdog timer can only be reset by
a power-on reset. When the watchdog feature is disabled, it can be used as an interval
timer and may generate an interrupt.
mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the
watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog
timer has a time-out period that ranges from a few s to a few seconds. Please refer to the
P89LPC9402 User manual for more details.
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
XTALWD
0
1
WDCON (A7H)
32
PRE2
Rev. 01 — 22 April 2009
PRESCALER
8-bit microcontroller with accelerated two-clock 80C51 core
PRE1
PRE0
Figure 16
SHADOW REGISTER
-
shows the watchdog timer in Watchdog
-
8-BIT DOWN
WDL (C1H)
COUNTER
WDRUN
P89LPC9402
WDTOF
© NXP B.V. 2009. All rights reserved.
WDCLK
002aae015
reset
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