P89LPC9402FBD,557 NXP Semiconductors, P89LPC9402FBD,557 Datasheet - Page 47

• Manufacturer Part Number: P89LPC9402FBD,557
• Description: IC 80C51 MCU FLASH 8K 64-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC9402FBD,557

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 64-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LED, POR, PWM, WDT
• Number Of I /o: 23
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935288631557

NXP Semiconductors
10. Dynamic characteristics
Table 13.
V
T
P89LPC9402_1
Product data sheet
Symbol
f
f
f
T
f
Glitch filter
t
t
External clock
t
t
t
t
Shift register (UART mode 0)
T
t
t
t
t
SPI interface
f
T
t
osc(RC)
osc(WD)
osc
CLKLP
gr
sa
CHCX
CLCX
CLCH
CHCL
QVXH
XHQX
XHDX
XHDV
SPI
SPILEAD
amb
DD
cy(clk)
XLXL
SPICYC
= 2.4 V to 3.6 V unless otherwise specified.
= 40 C to +85 C for industrial applications, unless otherwise specified.
Dynamic characteristics (12 MHz)
Parameter
internal RC oscillator frequency
internal watchdog oscillator
frequency
oscillator frequency
clock cycle time
low-power select clock frequency
glitch rejection time
signal acceptance time
clock HIGH time
clock LOW time
clock rise time
clock fall time
serial port clock cycle time
output data set-up to clock rising
edge time
output data hold after clock rising
edge time
input data hold after clock rising edge
time
input data valid to clock rising edge
time
SPI operating frequency
SPI cycle time
SPI enable lead time
slave
master
slave
master
slave
Rev. 01 — 22 April 2009
Conditions
see
P1.5/RST pin
any pin except
P1.5/RST
any pin except
P1.5/RST
see
see
see
see
see
see
see
see
see
see
20, 21,
see
22
P1.5/RST pin
8-bit microcontroller with accelerated two-clock 80C51 core
Figure
Figure
Figure 18
Figure 18
Figure 18
Figure 18
Figure 18
Figure 17
Figure 17
Figure 17
Figure 17
Figure 17
22
19,
21,
16T
13T
6
4
7.189
Min
320
125
150
250
CCLK
CCLK
83
50
33
33
0
0
0
cy(clk)
cy(clk)
-
-
-
-
-
-
-
[1][2]
Variable clock
T
T
T
cy(clk)
cy(clk)
cy(clk)
CCLK
CCLK
7.557
Max
520
12
50
15
8
8
8
0
-
-
-
-
-
-
-
-
-
+ 20
t
t
6
4
CHCX
CLCX
P89LPC9402
f
7.189
1333
1083
osc
Min
320
125
150
500
333
250
50
33
33
0
© NXP B.V. 2009. All rights reserved.
-
-
-
-
-
-
-
-
-
-
= 12 MHz Unit
7.557 MHz
Max
520
103
2.0
3.0
50
15
8
8
0
-
-
-
-
-
-
-
-
-
-
-
-
-
47 of 60
kHz
MHz
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns