P89LPC9402FBD,557 NXP Semiconductors, P89LPC9402FBD,557 Datasheet - Page 42

• Manufacturer Part Number: P89LPC9402FBD,557
• Description: IC 80C51 MCU FLASH 8K 64-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC9402FBD,557

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 64-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LED, POR, PWM, WDT
• Number Of I /o: 23
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935288631557

NXP Semiconductors
P89LPC9402_1
Product data sheet
7.28.5 Flash programming and erasing
7.28.6 In-circuit programming
7.28.7 In-application programming
7.28.8 In-system programming
Four different methods of erasing or programming of the flash are available. The flash may
be programmed or erased in the end-user application (IAP) under control of the
application’s firmware. Another option is to use the ICP mechanism. This ICP system
provides for programming through a serial clock - serial data interface. As shipped from
the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing
for the device to be programmed in circuit through the serial port. The flash may also be
programmed or erased using a commercially available EPROM programmer which
supports this device. This device does not provide for direct verification of code memory
contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire
user code space.
Remark: When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and flash
erase/program is blocked.
ICP is performed without removing the microcontroller from the system. The ICP facility
consists of internal hardware resources to facilitate remote programming of the
P89LPC9402 through a two-wire serial interface. Using commercially available
programmers, the NXP ICP facility has made ICP in an embedded application possible
with a minimum of additional expense in components and circuit board area. The ICP
function uses five pins. Only a small connector needs to be available to interface your
application to a commercial programmer in order to use this feature. Additional details
may be found in the P89LPC9402 User manual .
IAP is performed in the application under the control of the microcontroller’s firmware. The
IAP facility consists of internal hardware resources to facilitate programming and erasing.
The NXP IAP has made IAP in an embedded application possible without additional
components. Two methods are available to accomplish IAP. A set of predefined IAP
functions are provided in a Boot ROM and can be called through a common interface,
PGM_MTP. Several IAP calls are available for use by an application program to permit
selective erasing and programming of flash sectors, pages, security bits, configuration
bytes, and device ID. These functions are selected by setting up the microcontroller’s
registers before making a call to PGM_MTP at FF03H. The Boot ROM occupies the
program memory space at the top of the address space from FF00H to FEFFH, thereby
not conflicting with the user program memory space.
In addition, IAP operations can be accomplished through the use of four SFRs consisting
of a control/status register, a data register, and two address registers. Additional details
may be found in the P89LPC9402 User manual .
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LPC9402 through the serial port. This firmware is
provided by NXP and embedded within each P89LPC9402 device. The NXP ISP facility
has made ISP in an embedded application possible with a minimum of additional expense
Rev. 01 — 22 April 2009
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9402
© NXP B.V. 2009. All rights reserved.
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