P89LV51RD2FA,512 NXP Semiconductors, P89LV51RD2FA,512 Datasheet - Page 28

• Manufacturer Part Number: P89LV51RD2FA,512
• Description: IC 80C51 MCU 1024 RAM 44PLCC
• Manufacturer: NXP Semiconductors
• Series: 89LVr

Specifications of P89LV51RD2FA,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P89LV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Package: 44PLCC
• Device Core: 80C51
• Family Name: 89LV
• Maximum Speed: 40 MHz
• For Use With: 622-1017 - BOARD 44-ZIF PLCC SOCKET622-1008 - BOARD FOR LPC9103 10-HVSON
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 935274176512; P89LV51RD2FA; P89LV51RD2FA

NXP Semiconductors
P89LV51RB2_RC2_RD2_5
Product data sheet
Table 15.
Table 16.
Table 17.
Bit addressable; reset value: 0000 0000B; reset source(s): any reset.
Table 18.
Bit
M1
0
0
1
1
1
Bit
7
6
5
4
3
Bit
Symbol
TMOD - Timer/counter mode control register (address 89H) bit descriptions
TMOD - Timer/counter mode control register (address 89H) M1/M0 operating
mode
TCON - Timer/counter control register (address 88H) bit allocation
TCON - Timer/counter control register (address 88H) bit descriptions
Symbol
T1/T0
GATE
C/T
M0
0
1
0
1
1
Symbol
TF1
TR1
TF0
TR0
IE1
TF1
7
Rev. 05 — 15 December 2009
TR1
Operating mode
0
1
2
3
3
6
Description
Timer 1 overflow flag. Set by hardware on Timer/counter overflow.
Cleared by hardware when the processor vectors to Timer 1 Interrupt
routine, or by software.
Timer 1 Run control bit. Set/cleared by software to turn Timer/counter 1
on/off.
Timer 0 overflow flag. Set by hardware on Timer/counter overflow.
Cleared by hardware when the processor vectors to Timer 0 Interrupt
routine, or by software.
Timer 0 Run control bit. Set/cleared by software to turn Timer/counter 0
on/off.
Interrupt 1 Edge flag. Set by hardware when external interrupt 1
edge/low level is detected. Cleared by hardware when the interrupt is
processed, or by software.
Description
Bits controlling Timer1/Timer0
Gating control when set. Timer/counter ‘x’ is enabled only while ‘INTx’
INTx pin is HIGH and ‘TRx’ control pin is set. When cleared, Timer ‘x’
is enabled whenever ‘TRx’ control bit is set.
Gating Timer or Counter Selector cleared for Timer operation (input
from internal system clock). Set for Counter operation (input from ‘Tx’
input pin).
TF0
5
8048 timer ‘TLx’ serves as 5-bit prescaler
16-bit Timer/counter ‘THx’ and ‘TLx' are cascaded; there
is no prescaler.
8-bit auto-reload Timer/counter ‘THx’ holds a value which
is to be reloaded into ‘TLx’ each time it overflows.
(Timer 0) TL0 is an 8-bit Timer/counter controlled by the
standard Timer 0 control bits. TH0 is an 8-bit timer only
controlled by Timer 1 control bits.
(Timer 1) Timer/counter 1 stopped.
P89LV51RB2/RC2/RD2
TR0
4
8-bit microcontrollers with 80C51 core
IE1
3
IT1
2
© NXP B.V. 2009. All rights reserved.
IE0
1
28 of 76
IT0
0