LPC2923FBD100,551 NXP Semiconductors, LPC2923FBD100,551 Datasheet - Page 15

• Manufacturer Part Number: LPC2923FBD100,551
• Description: IC ARM9 MCU FLASH 256KB 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2900r

Specifications of LPC2923FBD100,551

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 125MHz
• Connectivity: CAN, I²C, LIN, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16K x 8
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 16x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC29
• Core: ARM968E-S
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935287115551

NXP Semiconductors
LPC2921_23_25_3
Product data sheet
found in the specific subsystem description. Some branch clocks have special protection
since they clock vital system parts of the device and should not be switched off. See
Section 6.15.5
Table 7.
Base clock
BASE_SAFE_CLK
BASE_SYS_CLK
BASE_PCR_CLK
BASE_IVNSS_CLK
Base clock and branch clock overview
for more details of how to control the individual branch clocks.
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 14 April 2010
Branch clock name
CLK_SAFE
CLK_SYS_CPU
CLK_SYS_SYS
CLK_SYS_PCRSS
CLK_SYS_FMC
CLK_SYS_RAM0
CLK_SYS_RAM1
CLK_SYS_GESS
CLK_SYS_VIC
CLK_SYS_PESS
CLK_SYS_GPIO0
CLK_SYS_GPIO1
CLK_SYS_GPIO5
CLK_SYS_IVNSS_A
CLK_SYS_MSCSS_A
CLK_SYS_DMA
CLK_SYS_USB
CLK_PCR_SLOW
CLK_IVNSS_APB
CLK_IVNSS_CANCA
CLK_IVNSS_CANC0
CLK_IVNSS_CANC1
CLK_IVNSS_I2C0
CLK_IVNSS_I2C1
CLK_IVNSS_LIN0
CLK_IVNSS_LIN1
ARM9 microcontroller with CAN, LIN, and USB
LPC2921/2923/2925
Parts of the device clocked
by this branch clock
watchdog timer
ARM968E-S and TCMs
AHB side of bridge in PCRSS
Embedded SRAM Controller 0
(16 kB)
Embedded SRAM Controller 1
(16 kB) (LPC2925 only)
General Subsystem
Vectored Interrupt Controller
Peripheral Subsystem
GPIO bank 0
GPIO bank 1
GPIO bank 5
GPDMA
PCRSS, CGU, RGU and PMU
logic clock
APB side of the IVNSS
CAN controller Acceptance
Filter
CAN channel 0
CAN channel 1
I
I
LIN channel 0
LIN channel 1
AHB bus infrastructure
Flash Memory Controller
AHB side of bridge of IVNSS
AHB side of bridge of MSCSS
USB registers
2
2
C0
C1
© NXP B.V. 2010. All rights reserved.
Remark
[1]
[2] [3]
[1] [4]
15 of 84